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Publications

Publications of Computer Architecture and VLSI Systems Laboratory (CARV)

Conferences (302)

Papers in Proceedings (full-paper reviewed)

  1. Katevenis, G., Ploumidis, M., & Marazakis, M. (2022). A framework for hierarchical single-copy MPI collectives on multicore nodes. IEEE International Conference on Cluster Computing (CLUSTER 2022), Heidelberg, Germany, 05-08 September (pp. 94-105).
  2. Biagioni, A., Cretaro, P., Frezza, O., Lo Cicero, F. , Lonardo, A. , Martinelli, M., Paolucci, P. S. , Pastorelli, E. , Simula, F., Turisini, M., Vicini, P. , Ammendola, R. , Bernier-Bruna, P., Chen, C., Derradji, S., Guez, S., Lagadec, P.A., Pichon, G., Walter, E., Cluzeau, Ch., de Gassowski, G., Gilliot, M., Hautreux, M., Mathieu, S., Taboada, H., Hoefler, T., Schneider, T., Barnaba, M., Brandino, G., Cozzini, S., De Giorgi, F., Poggi, M., Papaefstathiou, I., Tampouratzis, M., Kalisch, B., Krackhardt, U., Nuessle, M., Chrysos, N., Damianakis, A., Dollas, A., Gianioudis, M., Ioannou, A., Kallimanis, N., Katevenis, M.G.H., Loukas, H., & Marazakis, M. (2022). RED-SEA: Network Solution for Exascale Architectures. 25th Euromicro Conference on Digital System Design (DSD 2022), Maspalomas, Gran Canaria, Spain, Aug. 31–Sept. 2.
  3. Fatourou, P., Kallimanis, N., & Eleftherios , K.  (2021). Brief Announcement: Persistent Software Combining. 35th International Symposium on Distributed Computing (DISC 2021), (pp. 56:1-56:4).
  4. Wei, Y., Ben-David, N., Blelloch, G. E., Fatourou, P., Ruppert, E., & Sun, Y. (2021). Constant-time snapshots with applications to concurrent data structures. Proceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP '21), February (pp. 31-46).
  5. Chazapis, A., Acquaviva, J. Th., Bilas, A., Gardikis, G., Kozanitis, Ch., Louloudakis, S., Nguyen, H. N., Pinto, C., Scharl, A., & Soudris, D. (2021). EVOLVE: HPC and cloud enhanced testbed for extracting value from large-scale diverse data. CF '21: Proceedings of the 18th ACM International Conference on Computing Frontiers, May 11 - 13 (pp. 200-205). ACM.
  6. Koliogeorgi, K., Keddous, F. E., Masouros, D., Chazapis, A., Aubrun, M., Xydis, S., Bilas, A., Hugues, R., Acquaviva, J. Th., Nguyen, H. N., & Soudris, D. (2021). FPGA acceleration in EVOLVE’s Converged Cloud-HPC Infrastructure. 31st International Conference on Field-Programmable Logic and Applications (FPL 2021), Dresden, Germany, 30 Aug.-3 Sept. (pp. 376-377). IEEE.
  7. Chazapis, A., Politis, E., Kalaentzis, G., Kozanitis, Ch., & Bilas, A. (2021). H3: An Application-Level, Low-Overhead Object Store. High Performance Computing: ISC High Performance Digital 2021 International Workshops, Frankfurt am Main, Germany, June 24 – July 2 (vol. 1276 LNCS, pp. 174-188). Springer.
  8. Bajovic, D., Bakhtiarnia, A., Bravos, G., Brutti, A., Burkhardt, F., Cauchi, D., Chazapis, A., Cianco, C., Dall’Asen, N., Delic, V., Dimou, Ch., Djokic, D., Escobar-Molero, A., Esterle, L., Eyben, F., Farella, E., Festi, Th., Geromitsos, A., Giakoumakis, G., Hatzivasilis, G., Ioannidis, S., Iosifidis, A., Kallipolitou, Th., Kalogiannis, G., Kiousi, A., Kopanaki, D., Marazakis, M., Markopoulou, S., Muscat, A., Paissan, F., Pariente Lobo, T., Pavlovic, D., Raptis, Th.P., Ricci, E., Saez, B., Sahito, F., Scerri, K., Schuller, B., Simic, N., Spanoudakis, G., Tomasi, A., Triantafyllopoulos, A., Valerio, L., Villazán, J., Wang, Y., Xuereb, A., & Zammit, J. (2021). MARVEL: Multimodal Extreme Scale Data Analytics for Smart Cities Environments. Novi Sad, Serbia, 20-22 Sept. (pp. 143-147). IEEE.
  9. Papagiannis, A.P, Marazakis, M., & Bilas, A. (2021). Memory-Mapped I/O on Steroids. EuroSys '21: Proceedings of the Sixteenth European Conference on Computer Systems,  26-28 April (pp. 277-293). ACM.
  10. Xanthakis, G., Saloustros, G., Batsaras, N., & Papagiannis, A.P, Bilas, A. (2021). Parallax: Hybrid Key-Value Placement in LSM-based Key-Value Stores. Proceedings of the ACM Symposium on Cloud Computing (SoCC '21), Seattle WA USA, November 1 - 4 (pp. 305-318). ACM.
  11. Peng, B., Fatourou, P., & Palpanas, T. (2021). SING: Sequence Indexing Using GPUs. IEEE 37th International Conference on Data Engineering (ICDE 2021), Chania, Greece, 19-22 April (pp. 1883-1888). IEEE.
  12. Sfakianakis, Y.S, Marazakis, M., & Bilas, A. (2021). Skynet: Performance-driven Resource Management for Dynamic Workloads. 2021 IEEE 14th International Conference on Cloud Computing (CLOUD), 5-10 Sept. (pp. 527-539). Chicago, IL, USA: IEEE.
  13. Ben-David, N., Blelloch, G. E., Fatourou, P., Ruppert, E., Sun, Y., & Wei, Y. (2021). Space and Time Bounded Multiversion Garbage Collection. 35th International Symposium on Distributed Computing (DISC 2021), Dagstuhl, Germany(pp. 12:1-12:20).
  14. Sfakianakis, Y.S, Kanellou, E.K., Marazakis, M., & Bilas, A. (2021). Trace-Based Workload Generation and Execution. Euro-Par 2021: parallel processing 27th International Conference on Parallel and Distributed Computing, Lisbon, Portugal, September 1–3 (vol. 1282 LNCS, pp. 37-54). Springer.
  15. Attiya, H., Ben-Baruch, O., Fatourou, P., Hendler, D., & Eleftherios , K.  (2020). Brief Announcement: Tracking in Order to Recover: Detectable Recovery of Lock-Free Data Structures. SPAA '20: Proceedings of the 32nd ACM Symposium on Parallelism in Algorithms and Architectures, Philadelphia, PA, USA, July 2020 (pp. 503-505).
  16. Sfakianakis, Y.S, Marazakis, M., & Bilas, A. (2020). DyRAC: Cost-aware Resource Assignment and Provider Selection for Dynamic Cloud Workloads. Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2020).
  17. Peng, B., Fatourou, P., & Palpanas, T. (2020). MESSI: In-Memory Data Series Indexing.  IEEE 36th International Conference on Data Engineering (ICDE 2020), Dallas, TX, USA, 20-24 April 2020 (pp. 337-348). IEEE.
  18. Pham, K., Koch, D., Vaishnav, A., Georgopoulos, K., Malakonakis, P., Ioannou, A., & Mavroidis, I. (2020). Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation. International Conference on Field-Programmable Technology (ICFPT 2020), Maui, Hawaii, US.
  19. Papagiannis, A., Xanthakis, G., Saloustros, G., Marazakis, M., & Bilas, A. (2020). Optimizing Memory-mapped I/O for Fast Storage Devices. Proceedings of the 2020 USENIX Annual Technical Conference (USENIX ATC'20), Boston, MA, USA, July 2020.
  20. Psistakis, A., Chrysos, N., Chaix, F., Asiminakis, M., Giannioudis, M., Xirouchakis, P., Papaefstathiou, V., & Katevenis, M.G.H. (2020). PART: Pinning Avoidance in RDMA Technologies. 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2020),  Hamburg, Germany, 24-25 Sept. (pp. 1-8). IEEE.
  21. Attiya, H., Fatourou, P., Hans, S., & Kanellou, E.K. (2020). Staleness and Local Progress in Transactional Memory. 8th International Conference on Networked Systems (NETYS 2020), Marrakech, Morocco, June 3–5, 2020 (vol. 12129 LNCS, pp. 227-243). Springer.
  22. Vardas, I., Ploumidis, M., & Marazakis, M. (2020). Towards Communication Profile, Topology and Node Failure Aware Process Placement. IEEE 32nd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Porto, Portugal, 2020(pp. 241-248).
  23. Pavlidakis, M., Mavridis, S., Chrysos, N., & Bilas, A. (2020). TReM: A Task Revocation Mechanism for GPUs. 22nd IEEE International Conference on High Performance Computing and Communications (IEEE HPCC-2020), 14-16 December 2020.
  24. Taffoni, G., Tornatore, L., Goz, D., Ragagnin, A., Bertocco, S., Coretti, I., Marazakis, M., Chaix, F., Ploumidis, M., Katevenis, M.G.H., Panchieri, R., & Perna, G.  (2019). Towards Exascale: Measuring the Energy Footprint of Astrophysics HPC Simulations. 15th International Conference on eScience (eScience 2019),  San Diego, CA, USA, USA, (pp. 403-412). IEEE.
  25. Fatourou, P., Kallimanis, N., & Kanellou, E.K. (2019). An Efficient Universal Construction for Large Objects. 23rd International Conference on Principles of Distributed Systems (OPODIS 2019), December 2019. Neuchatel, Switzerland.
  26. Kolokasis, I.G., & Pratikakis , P. (2019). Cut to Fit: Tailoring the Partitioning to the Computation. GRADES-NDA'19: Proceedings of the 2nd Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA), Amsterdam Netherlands, June, Article No.: 9 (pp. 1-10).
  27. Didona, D., Fatourou, P., Guerraoui, R.G, Wang, J., & Zwaenepoel, W. (2019). Distributed Transactional Systems Cannot Be Fast. 31st ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2019), Phoenix, AZ, USA, 22-24 June, 2019 (pp. 369-380).
  28. Pitsis, G., Tsagkatakis, G., Kozanitis, Ch., Kalomoiris, I., Ioannou, A., Dollas, A., Katevenis, M.G.H., & Tsakalides, P. (2019). Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-fpga Platforms. 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2019) , Brighton, United Kingdom, United Kingdom, 12-17 May 2019 (pp. 3917-3921). IEEE.
  29. Fatourou, P., Papavasileiou, E., & Ruppert, E. (2019). Persistent Non-Blocking Binary Search Trees Supporting Wait-Free Range Queries. 31st ACM Symposium on Parallelism in Algorithms and Architectures (SPAA 2019), Phoenix, AZ, USA, 22-24 June, 2019 (pp. 275-286).
  30. Alachiotis , N., Vatsolakis, C., Chrysos , G., & Pnevmatikatos, D. (2018). Accelerated Inference of Positive Selection on Whole Genomes. 28th International Conference on Field Programmable Logic and Applications (FPL 2018), 27-31 Aug. 2018. Dublin, Ireland, Ireland: IEEE.
  31. Giannopoulos, D., Chrysos, N., Mageiropoulos, E., Vardas, G., Tzanakis, L., & Katevenis, M.G.H. (2018). Accurate Congestion Control for RDMA Transfers. Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018), Turin, Italy, 4-5 Oct. 2018. IEEE.
  32. Papagiannis, A., Saloustros, G., Gonzalez-Ferez, P., & Bilas, A. (2018). An Efficient Memory-Mapped Key-Value Store for Flash Storage. Proceedings of the ACM Symposium on Cloud Computing (SoCC '18), Carlsbad, CA, USA — October 11 - 13, 2018 , (pp. 490-502). ACM.
  33. Fatourou, P., Kallimanis, N., & Ropars, Th. (2018). An Efficient Wait-free Resizable Hash Table. Proceedings of the 30th on Symposium on Parallelism in Algorithms and Architectures (SPAA '18), Vienna, Austria, July 16 - 18, 2018 (pp. 111-120). ACM.
  34. Ustiugov, D., Daglis, A., Picorel, J., Sutherland, M., Bugnion, E., Falsafi, B., & Pnevmatikatos, D. (2018). Design Guidelines for High-Performance SCM Hierarchies. 4th International Symposium on Memory Systems (MEMSYS 2018), Old Town Alexandria, VA, USA, October 1-4, 2018. ACM.
  35. Bielski , M., Syrigos, I. , Katrinis, K., Syrivelis, D., Reale, A., Theodoropoulos, D., Alachiotis , N., Pnevmatikatos, D., Pap, E.H., Zervas, G., Mishra, V., Rigo, A., Zazo, J. F., Lopez-Buedo, S., Torrents, M., Zyulkyarov, F., Enrico, M., & González De Dios, O. (2018). dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter.  Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 19-23 March 2018. Dresden, Germany: IEEE.
  36. Chrysos, N., Kanellou, E.K., Mavridis, S., & Sfakianakis, Y.S, Bilas, A. (2018). GPU Provisioning: The 80 - 20 Rule. Proceedings of the 24th International European Conference on Parallel and Distributed Computing (EuroPar 2018), Turin, Italy, 27-31 August, 2018 (vol. 11014 LNCS, pp. 352-364). Springer.
  37. Peng, B., Fatourou, P., & Palpanas, T. (2018). ParIS: The Next Destination for Fast Data Series Indexing and Query Answering. IEEE International Conference on Big Data (Big Data 2018), Seattle, WA, USA, 10-13 Dec. 2018 (pp. 791-800). IEEE.
  38. Kachris, C., Soudris, D., Mavridis, S., Pavlidakis, M., Symeonidou, C., Kozanitis, Ch., Bilas, A., Fenacci, D., Bogaraju, S.V, Vandierendonck, H., & Nikolopoulos, D.S. (2018). The VINEYARD integrated framework for hardware accelerators in the cloud . Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2018), 15-19 July (pp. 236-243). Samos, Greece: ACM.
  39. Syrivelis, D., Reale, A., Katrinis, K., Syrigos, I. , Bielski , M., Theodoropoulos, D., Pnevmatikatos, D., & Zervas, G. (2017). A Software-defined Architecture and Prototype for Disaggregated Memory Rack Scale Systems. International Conference On Embedded Computer Systems: Architectures, Modeling And Simulation (SAMOS 2017) , Samos, Greece, 17-20 July (pp. 1-8).
  40. Bozikas, D., Alachiotis , N., Pavlidis , P., Sotiriades, E., & Dollas, A. (2017). Deploying FPGAs to Future-proof Genome-wide Analyses based on Linkage Disequilibrium. 26th International Conference on Field Programmable Logic and Applications (FPL 2017),  Ghent, Belgium, 4 - 8 September .
  41. Katsogridakis , P., Papagiannaki, S., & Pratikakis , P. (2017). Execution of Recursive Queries in Apache Spark. Euro-Par 2017: Parallel Processing: 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28 – September 1 (vol. 10417 LNCS, pp. 289-302). Springer .
  42. Theodoropoulos, D., Alachiotis , N., & Pnevmatikatos, D. (2017). FPGA-based Evaluation Platform for Disaggregated Computing. International Conference On Embedded Computer Systems: Architectures, Modeling And Simulation (SAMOS 2017), Samos, Greece, 17-20 July (pp. 1-8).
  43. Mouzakitis, A., Pinto, C., Nikolaev, N., Rigo, A., Raho, D., Aronis, B., & Marazakis, M. (2017). Lightweight and Generic RDMA Engine Para-Virtualization for the KVM Hypervisor. Proceedings of the 2017 International Conference on High Performance Computing & Simulation (HPCS 2017) , Genoa, Italy, 17-21 July 2017 (pp. 17-21). IEEE.
  44. Fatourou, P., & Kallimanis, N. (2017). Lock Oscillation: Boosting the Performance of Concurrent Data Structures. Proceedings of the 21st International Conference on Principles of Distributed Systems (OPODIS’17), Lisboa, Portugal, December 2017.
  45. Ammendola, R. , Biagioni, A., Cretaro, P., Frezza, O., Lo Cicero, F. , Lonardo, A. , Martinelli, M., Paolucci, P. S. , Pastorelli, E. , Pisani, F., Simula, F., Vicini, P. , J. Navaridas, J. , Chaix, F., Chrysos, N., Katevenis, M.G.H., & Papaefstathiou, V. (2017). Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project. Journal of Physics: Conference Series (JPCS), vol. 898, track 6, no.082045.
  46. Vasilakis, E., Sourdis, I., Papaefstathiou, V., Psathakis, A., & Katevenis , M. (2017). Modeling Energy-Performance Tradeoffs in ARM big.LITTLE Architectures. Proceedings of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017) , Thessaloniki, Greece, 25 - 27 September.
  47. Malek, A., Vasilakis, E., Papaefstathiou, V., Trancoso, P., & Sourdis, I. (2017). Odd-ECC: On-demand DRAM Error Correcting Codes. Proceedings of the International Symposium on Memory Systems (MEMSYS ), Washington DC, USA, 2-5 October .
  48. Rigo, A., Pinto, C., Pouget, K., Raho, D., Dutoit, D., Martinez, P.Y., Doran, Ch., Benini, L., Mavroidis, I., Marazakis, M., Bartsch, V., Lonsdale, G., Pop, A. , Goodacre, J., Colliot, A. , Carpenter, P., & Radojković, P. , Pleiter, D. , Drouin, D. , de Dinechin, B.D.  (2017). Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach. 2017 Euromicro Conference on Digital System Design (DSD), Vienna, Austria, 30 Aug.-1 Sept. (pp. 486-493). IEEE.
  49. Theodoropoulos, D., Reale, A., Syrivelis, D., Bielski , M., Alachiotis , N., & Pnevmatikatos, D. (2017). REMAP: Remote mEmory Manager for disAggregated Platforms. IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Milan, Italy, 10-12 July. IEEE.
  50. Drumond, M., Daglis, A., Mirzadeh, N., Ustiugov, D., Picorel, J., Falsafi, B., Grot, B., & Pnevmatikatos, D. (2017). The Mondrian Data Engine. Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA '17 ), Toronto, ON, Canada, June 24 - 28 (pp. 639-651 ). ACM.
  51. Ammendola, R. , Biagioni, A., Cretaro, P., Frezza, O., Lo Cicero, F. , Lonardo, A. , Martinelli, M., Paolucci, P. S. , Pastorelli, E. , Simula, F., Vicini, P. , Taffoni, G., Pascual, J.A. , J. Navaridas, J. , Luján, M., Goodacre, J., Chrysos, N., & Katevenis, M.G.H. (2017). The Next Generation of Exascale-Class Systems: The ExaNeSt Project. 2017 Euromicro Conference on Digital System Design (DSD), 30 Aug.-1 Sept.. Vienna, Austria: IEEE.
  52. Alachiotis , N., Theodoropoulos, D., & Pnevmatikatos, D. (2017). Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study. 27th International Conference on Field Programmable Logic and Applications (FPL 2017), Ghent, Belgium, 4-8 Sept.. IEEE.
  53. Mavridis, S., Pavlidakis, M., Kozanitis, Ch., Chrysos, N., Stamoulias, I., Kachris, C., Soudris, D., & Bilas, A. (2017). VineTalk: Simplifying Software Access and Sharing of FPGAs in Datacenters. 27th International Conference on Field Programmable Logic and Applications (FPL 2017), Ghent, Belgium, 4 - 8 September (pp. 1-4). IEEE.
  54. Mazumdar, S., Ayguade, E., Bettin, N., Bueno, J., Ermini, S., Filgueras, A, Jimenez-Gonzalez, D., Alvarez-Martinez, C., Martorell, X., Montefoschi, F., Oro, D., Pnevmatikatos, D., Rizzo, A., Theodoropoulos, D., & Giorgi , R. (2016). AXIOM: A Hardware-Software Platform for Cyber Physical Systems. 19th Euromicro Conference on Digital System Design (DSD 2016), Limassol, Cyprus, 31 Aug.-2 Sept. (pp. 539-546). IEEE.
  55. Zakkak, F. S., & Pratikakis , P. (2016). Building a Java™ Virtual Machine for Non-Cache-Coherent Many-core Architectures. Proceedings of the 14th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2016) , Lugano, Switzerland , August 29 - September 02. ACM.
  56. Zakkak, F. S., & Pratikakis , P. (2016). DiSquawk: 512 cores, 512 memories, 1 JVM. Proceedings of the 13th International Conference on Principles and Practices of Programming on the Java Platform: Virtual Machines, Languages, and Tools (PPPJ '16), Lugano, Switzerland, 29 Aug. - 2 Sep. (12 pages). ACM.
  57. Fatourou, P., Kallimanis, N., Kanellou, E.K., Makridakis, O., & Symeonidou, C. (2016). Efficient Distributed Data Structures for Future Many-core Architectures. Proceedings of the 22nd International Conference on Parallel and Distributed Systems (ICPADS 2016), Wuhan, China, 13-16 December (pp. 835-842). IEEE.
  58. Marazakis, M., Goodacre, J., Fuin, D., Carpenter, P., Thomson, J., Matus, E., Bruno, A., Stenstrom, P., Martin, J., Durand, Y., & Dor, I.  (2016). EUROSERVER: Share-Anything Scale-Out Micro-Server Design. Proceedings of the Design, Automation, and Test in Europe Conference (DATE 2016), Dresden, Germany, 14-18 March (pp. 678-683). IEEE.
  59. Papakonstantinou, N., Zakkak, F. S., & Pratikakis , P. (2016). Hierarchical Parallel Dynamic Dependence Analysis for Recursively Task-Parallel Programs. 30th IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2016), Chicago, IL, USA, 23-27 May . IEEE.
  60. Pavlidakis, E., Mavridis, S., Saloustros, G., & Bilas, A. (2016). KVFS: An HDFS Library over NoSQL Databases. Proceedings of the 6th International Conference on Cloud Computing and Services Science - Volume 1 and 2, Rome, Italy, April 23-25 (pp. 360-367). ACM.
  61. Katrinis, K., Zervas, G., Pnevmatikatos, D., Syrivelis, D., Alexoudi, T., Theodoropoulos, D., Raho, D., Pinto, C., Espina, F., Lopez-Buedo, S., Chen, Q., Nemirovsky, M., Roca, D. , Klos, H., & Berends, T. (2016). On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision. European Conference on Networks and Communications (EuCNC 2016), Athens, Greece, 27-30 June (pp. 235-239). IEEE.
  62. Katrinis, K., Syrivelis, D., Pnevmatikatos, D., Zervas, G., Theodoropoulos, D., Koutsopoulos, I., Hasharoni, K., Raho, D., Pinto, C., Espina, F., Lopez-Buedo, S., Chen, Q., Nemirovsky, M., Roca, D. , Klos, H., & Berends, T. (2016). Rack-scale disaggregated cloud data centers: The dReDBox project vision. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 14-18 March (pp. 690-695). IEEE.
  63. Katevenis , M., Chrysos, N., Marazakis, M., Mavroidis, I., Chaix, F., Kallimanis, N., J. Navaridas, J. , Goodacre, J., Vicini, P. , Biagioni, A., Paolucci, P. S. , Lonardo, A. , Pastorelli, E. , Lo Cicero, F. , Ammendola, R. , Hopton, P., Coates, P., Taffoni, G., Cozzini, S., Kersten, M., Zhang, Y., Sahuquillo, J., Lechago, S. , Pinto, C., Lietzow, B., Everett, D., & Perna, G.  (2016). The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems. 19th Euromicro Conference on Digital System Design (DSD 2016), Limassol, Cyprus, 31 Aug.-2 Sept. (pp. 60-67). IEEE.
  64. Papagiannis, A., Saloustros, G., Gonzalez-Ferez, P., & Bilas, A. (2016). Tucana: design and implementation of a fast and efficient scale-up key-value store. Proceedings of the 2016 USENIX Annual Technical Conference (USENIX ATC '16), Denver, CO, USA, June 22-24 (pp. 537-550). ACM.
  65. Charitopoulos, G., Pnevmatikatos, D., Santambrogio, M.D., Papadimitriou, K., & Pau, D. (2015). A run-time system for partially reconfigurable FPGAs: The case of STMicroelectronics SPEAr board. PARCO 2015, Edinburgh, Scotland, UK, 1–4 September (pp. 553-562).
  66. Psathakis, A., Papaefstathiou, V., Chrysos, N., Chaix, F., Vasilakis, E., Pnevmatikatos, D., & Katevenis , M. (2015). A systematic evaluation of emerging mesh-like CMP NoCs. ANCS '15 Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, Oakland, CA USA, 7-8 May (pp. 159-170).
  67. Charitopoulos, G., George, , Papadimitriou, K., & Pnevmatikatos, D. (2015). Hardware Task Scheduling for Partially Reconfigurable FPGAs. Applied Reconfigurable Computing: 11th International Symposium (ARC 2015), Lecture Notes in Computer Science, Bochum, Germany, April 13-17 (vol. 9040, pp. 487-498). Springer.
  68. Gonzalez-Ferez, P., & Bilas, A. (2015). Reducing CPU and network overhead for small I/O requests in network storage protocols over raw Ethernet.  31st Symposium on Mass Storage Systems and Technologies (MSST 2015), Santa Clara, California, USA, 30 May - 5 June (pp. 1-12). (pdf).
  69. Saloustros, G., & Magoutis, K. (2015). Rethinking HBase: Design and Implementation of an Elastic Key-Value Store over Log-Structured Local Volumes. 14th International Symposium on Parallel and Distributed Computing (ISPDC 2015) ,  Limassol, Cyprus, 29 June - 2 July (pp. 225 - 234).
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  128. Singh, K., Curtis-Maury, M., McKee, S.A., Blagojevic, F., Nikolopoulos, D.S., & Supinski, B.R.de, Schulz, M. (2010). Comparing scalability prediction strategies on an SMP of CMPs. Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I, Ischia, Italy, (pp. 143-155). Berlin, Heidelberg: Springer-Verlag (3-642-15276-7, 978-3-642-15276-4).
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  134. Kavadias, S.G., Katevenis, M.G.H., Zampetakis, M., & Nikolopoulos, D.S. (2010). On-chip communication and synchronization mechanisms with cache-integrated network interfaces. CF '10: Proceedings of the 7th ACM international conference on Computing frontiers, Bertinoro, Italy, (pp. 217-226). New York, NY, USA: ACM (978-1-4503-0044-5).
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  138. Tzenakis, G., Kapelonis, K., Alvanos, M., Koukos, K., Nikolopoulos, D.S., & Bilas, A. (2010). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the cell processor. 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, Pisa, 25 January 2010 through 27 January 2010 (vol. 5952 LNCS, pp. 307-321). (03029743; 3642115144 (ISBN); 9783642115141 (ISBN)).
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  141. Schneider, Sc., Yeom, J.S., Rose, B., Linford, J.C., Sandu, A., & Nikolopoulos, D.S. (2009). A comparison of programming models for multiprocessors with explicitly managed memory hierarchies. Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming, San Jose, CA, USA, (pp. 131-140). ACM New York, NY, USA.
  142. Kyriakoulakos, K., & Pnevmatikatos, D. (2009). A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. FPL 09: 19th International Conference on Field Programmable Logic and Applications, Prague, 31 August 2009 through 2 September 2009 (pp. 193-198). (9781424438921 (ISBN)).
  143. Yeom, J.S., & Nikolopoulos, D.S. (2009). A Runtime Framework for Optimizing Multi-Dimensional Array Accesses on Multi-core Processors. Proceedings of the First International Workshop on Programming Models for Emerging Architectures (PMEA), held in conjunction with the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, USA.
  144. Rafique, M.M., Rose, B., Butt, A.R., & Nikolopoulos, D.S. (2009). CellMR: A framework for supporting mapreduce on asymmetric cell-based clusters. IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, Miami, Florida, USA, (pp. 1-12). Washington, DC, USA: IEEE Computer Society (978-1-4244-3751-1).
  145. Afratis, P., Galanakis, C., Sotiriades, E., Mplemenos, G.G., Chrysos, G., Papaefstathiou, I., & Pnevmatikatos, D. (2009). Design and implementation of a database filter for BLAST acceleration. 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, Nice, 20 April 2009 through 24 April 2009 (pp. 166-171). (15301591; 9783981080155 (ISBN)).
  146. Kontos, D., Papaefstathiou, I., & Pnevmatikatos, D. (2009). Design space exploration of reconfigurable systems for calculating flying object"s optimal noise reduction paths. FPL 09: 19th International Conference on Field Programmable Logic and Applications, Prague, 31 August 2009 through 2 September 2009 (pp. 282-287). (9781424438921 (ISBN)).
  147. Brzezniak, M., Meyer, N., Flouris, M.D., & Bilas, A. (2009). Evaluation of Custom vs Commodity Technology-based Storage Elements. 3rd CoreGRID Workshop on Grid Middleware 2008, (pp. 1-9).
  148. Mangas, E., & Bilas, A. (2009). FLASH: Fine-grained localization in wireless sensor networks using acoustic sound transmissions and high precision clock synchronization. 2009 29th IEEE International Conference on Distributed Computing Systems Workshops, ICDCS, 09, Montreal, QC, 22 June 2009 through 26 June 2009 (pp. 289-298). (9780769536606 (ISBN)).
  149. Kalokairinos, G., Papaefstathiou, V., Nikiforos, G., Kavadias, S.G., Katevenis, M.G.H., Pnevmatikatos, D., & Yang, X. (2009). FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009, Samos, 20 July 2009 through 23 July 2009 (pp. 149-156). (9781424445011 (ISBN)).
  150. Panagiotakis, G., Flouris, M.D., & Bilas, A. (2009). Reducing disk I/O performance sensitivity for large numbers of sequential streams. 2009 29th IEEE International Conference on Distributed Computing Systems Workshops, ICDCS, 09, Montreal, QC, 22 June 2009 through 26 June 2009 (pp. 22-31). (9780769536606 (ISBN)).
  151. Blagojevic, F., Iancu, C., Yelick, K.A., Curtis-Maury, M., Nikolopoulos, D.S., & Rose, B. (2009). Scheduling dynamic parallelism on accelerators. Proceedings of the 6th Conference on Computing Frontiers, Ischia, Italy, 18-20 May (pp. 161-170). ACM.
  152. Fatourou, P., & Kallimanis, N. (2009). The RedBlue adaptive universal constructions. DISC '09: Proceedings of the 23rd international conference on Distributed computing, Elche, Spain, (pp. 127-141). Berlin, Heidelberg: Springer-Verlag (3-642-04354-2, 978-3-642-04354-3).
  153. Passas, S., Magoutis, K., & Bilas, A. (2009). Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design. ICS '09: Proceedings of the 23rd international conference on Supercomputing, Yorktown Heights, NY, USA, (pp. 214-224). New York, NY, USA: ACM (978-1-60558-498-0).
  154. Luna, J., Dikaiakos, M., Gjermundrod, H., Flouris, M.D., Marazakis, M., & Bilas, A. (2009). Using gLite to Implement a Secure ICGrid. In CoreGRID Workshop on Grid Middleware 2008, June (pp. 1-15).
  155. Sebepou, Z., Magoutis, K., Marazakis, M., & Bilas, A. (2008). A Comparative Experimental Study of Parallel File Systems for Large-Scale Data Processing. LASCO, Boston, MA, USA, June 23.
  156. Luna, J., Flouris, M.D., Marazakis, M., Bilas, A., Dikaiakos, M., Gjermundrod, H., & Kyprianou, Th. (2008). A Data-Centric Security Analysis Of ICGrid. April 2008 (pp. 197-208).
  157. Nikiforos, G., Kalokairinos, G., Papaefstathiou, V., Kavadias, S.G., Pnevmatikatos, D., & Katevenis, M.G.H. (2008). A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. 6th HiPEAC Industrial Workshop, 26 November.
  158. Luna, J., Flouris, M.D., Marazakis, M., Bilas, A., Stagni, F., Forti, A., Ghiselli, A., Magnoni, L., & Zappi, R. (2008). An Analysis of Security Services in Grid Storage Systems. June 25-26 (pp. 171-185). Dresden, Germany.
  159. Brzezniak, M., Meyer, N., Flouris, M.D., Lachaize, R., & Bilas, A. (2008). Analysis of Grid Storage Element Architectures: High-end Fiber-Channel vs. Emerging Cluster-based Networked Storage. (pp. 187-201).
  160. Chrysos, N.I., & Dimitrakopoulos, G. (2008). Backlog-aware crossbar schedulers: A new algorithm and its efficient hardware implementation. 16th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects, Stanford, CA, 26 August 2008 through 28 August 2008 (pp. 67-74). (15504794; 9780769533803 (ISBN)).
  161. Aji, A.M., Feng, W.Ch., Blagojevic, F., & Nikolopoulos, D.S. (2008). Cell-SWat: modeling and scheduling wavefront computations on the cell broadband engine. CF '08: Proceedings of the 2008 conference on Computing frontiers, Ischia, Italy, (pp. 13-22). New York, NY, USA: ACM (978-1-60558-077-7).
  162. Luna, J., Dikaiakos, M., Kyprianou, Th., Bilas, A., & Marazakis, M. (2008). Data privacy considerations in Intensive Care Grids. 6th Annual HealthGrid Conference - Global HealthGrid: E-Science Meets Biomedical Informatics, HealthGrid 2008, Chicago, IL, 2 June 2008 through 4 June 2008 (vol. 138, pp. 178-187). (09269630; 9781586038748 (ISBN)).
  163. Passas, S., Kotsis, G., Karlsson, S., & Bilas, A. (2008). Exploiting spatial parallelism in ethernet-based cluster interconnects. 
  164. Dimitrakopoulos, G., Chrysos, N.I., & Galanopoulos, K. (2008). Fast arbiters for on-chip network switches. 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, 12 October 2008 through 15 October 2008 (pp. 664-670). (9781424426584 (ISBN)).
  165. Olesinski, W., Eberle, H., Gura, N., & Chrysos, N.I. (2008). Flow control in Output Buffered Switch with Input Groups. In Proceedings of the IEEE High Performance Switching and Routing (HPSR08), Shanghai, China, May 15-17 (pp. 6-12).
  166. Flouris, M.D., Lachaize, R., & Bilas, A. (2008). Orchestra: Extensible Block-Level Support for Resource and Data Sharing in Networked Storage Systems. Parallel and Distributed Systems, 2008. ICPADS '08. 14th IEEE International Conference on, December 2008 (pp. 237-244). (1521-9097).
  167. Luna, J., Flouris, M.D., Marazakis, M., & Bilas, A. (2008). Providing security to the Desktop Data Grid. 
  168. Blagojevic, F., Curtis-Maury, M., Jae-Seung, Y., Schneider, Sc., & Nikolopoulos, D.S. (2008). Scheduling Asymmetric Parallelism on a PlayStation3 Cluster. Cluster Computing and the Grid, 2008. CCGRID '08. 8th IEEE International Symposium on, Lyon, France, May (pp. 146-153).
  169. Katevenis, M.G.H. (2008). Towards unified mechanisms for inter-processor communication. Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on, (pp. iii-iii).
  170. Andrikos, N., Lavagno, L., Pandini, D., & Sotiriou, Ch.P. (2007). A fully-automated desynchronization flow for synchronous circuits. 2007 44th ACM/IEEE Design Automation Conference, DAC '07, San Diego, CA, 4 June 2007 through 8 June 2007 (pp. 982-985). (0738100X; 1595936270 (ISBN); 9781595936271 (ISBN)).
  171. Dimopoulos, V., Papaefstathiou, I., & Pnevmatikatos, D. (2007). A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems. Proceedings of 2007 International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (IC-SAMOS 2007), Samos, Greece, 16-19 July (pp. 186-193).
  172. Mihelogiannakis, G., Pnevmatikatos, D., & Katevenis, M.G.H. (2007). Approaching ideal NoC latency with pre-configured routes. NOCS 2007: First International Symposium on Networks-on-Chip, Princeton, NJ, 7 May 2007 through 9 May 2007 (pp. 153-162). (0769527736 (ISBN); 9780769527734 (ISBN)).
  173. Passas, G., & Katevenis, M.G.H. (2007). Asynchronous operation of bufferless crossbars. 2007 IEEE Workshop on High Performance Switching and Routing, HPSR, Brooklyn, NY, 30 May 2007 through 1 June 2007 (pp. 187-192). (1424412064 (ISBN); 9781424412068 (ISBN)).
  174. Chrysos, N.I. (2007). Congestion management for non-blocking clos networks. ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems, Orlando, Florida, USA, (pp. 117-126). New York, NY, USA: ACM (978-1-59593-945-6).
  175. Chrysos, N.I., & Katevenis, M.G.H. (2007). Crossbars with minimally-sized crosspoint buffers. 2007 IEEE Workshop on High Performance Switching and Routing, HPSR, Brooklyn, NY, 30 May 2007 through 1 June 2007 (pp. 180-186). (1424412064 (ISBN); 9781424412068 (ISBN)).
  176. Papaefstathiou, I., & Papaefstathiou, V. (2007). Memory-Efficient 5D Packet Classification At 40 Gbps. INFOCOM 2007. 26th IEEE International Conference on Computer Communications. IEEE, Anchorage Alaska, USA, 6-12 may (pp. 1370-1378). (0743-166X).
  177. Karlsson, S., Passas, S., Kotsis, G., & Bilas, A. (2007). MultiEdge: An edge-based communication subsystem for scalable commodity servers. 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007. (1424409101 (ISBN); 9781424409105 (ISBN)).
  178. Marazakis, M., Papaefstathiou, V., & Bilas, A. (2007). Optimization and bottleneck analysis of network block I/O in commodity storage systems. (pp. 33-42).
  179. Papaefstathiou, V., Pnevmatikatos, D., Marazakis, M., Kalokairinos, G., Ioannou, A., Papamichael, M., Kavadias, S.G., Mihelogiannakis, G., & Katevenis, M.G.H. (2007). Prototyping efficient interprocessor communication mechanisms. 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007, Samos, 16 July 2007 through 19 July 2007 (pp. 26-33). (1424410584 (ISBN); 9781424410583 (ISBN)).
  180. Német, Z., Flouris, M.D., Lachaize, R., & Bilas, A. (2007). Support for Automatic Diagnosis and Dynamic Configuration of Scalable Storage Systems. Dresden, Germany, August 29-September 1 (vol. 4375/2007, pp. 15-21). Springer Berlin / Heidelberg.
  181. Papaefstathiou, V., & Papaefstathiou, I. (2006). A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. DATE '06: Proceedings of the conference on Design, automation and test in Europe, Munich, Germany, (pp. 112-117). 3001 Leuven, Belgium, Belgium: European Design and Automation Association (3-9810801-0-6).
  182. Kassapaki, E., Mattheakis, P.M., & Sotiriou, Ch.P. (2006). Actual-delay circuits on FPGA: Trading-off LUTs for speed. 2006 International Conference on Field Programmable Logic and Applications, FPL, Madrid, 28 August 2006 through 30 August 2006 (pp. 599-604). (142440312X (ISBN); 9781424403127 (ISBN)).
  183. Papaefstathiou, V., Kalokairinos, G., Ioannou, A., Papamichael, M., Mihelogiannakis, G., Kavadias, S.G., Vlachos, E., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication. In the 2nd HiPEAC Industrial Workshop on Embedded Computing, Eindhoven, Netherlands, 17 October.
  184. Papaefstathiou, I., & Papaefstathiou, V. (2006). An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks. Proc. IEEE International Conference on Communications (ICC2006), Istanbul, Turkey, 11-15 June.
  185. Marazakis, M., Xinidis, K., Papaefstathiou, V., & Bilas, A. (2006). Efficient remote block-level I/O over an RDMA-capable NIC. 20th Annual International Conference on Supercomputing, ICS 2006, Cairns, Queensland, 28 June 2006 through 1 July 2006 (pp. 97-106). (1595932828 (ISBN); 9781595932822 (ISBN)).
  186. Marazakis, M., Papaefstathiou, V., Kalokairinos, G., & Bilas, A. (2006). Experiences from debugging a PCIX-based RDMA-capable NIC. 2006 IEEE International Conference on Cluster Computing, Cluster 2006, Barcelona, 25 September 2006 through 28 September 2006. (15525244; 1424403286 (ISBN); 9781424403288 (ISBN)).
  187. Christodoulopoulou, R., Manassiev, K., Bilas, A., & Amza, C. (2006). Fast and transparent recovery for continuous availability of cluster-based servers. 2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP '06, New York, NY, 29 March 2006 through 31 March 2006 (vol. 2006, pp. 221-229). (1595931899 (ISBN); 9781595931894 (ISBN)).
  188. Passas, G., & Katevenis, M.G.H. (2006). Packet mode scheduling in buffered crossbar (CICQ) switches. 2006 Workshop on High Performance Switching and Routing, HPSR 2006, Poznan, 7 June 2006 through 9 June 2006 (pp. 105-112). (0780395697 (ISBN); 9780780395695 (ISBN)).
  189. Sourdis, I., Dimopoulos, V., Pnevmatikatos, D., & Vassiliadis, S. (2006). Packet pre-filtering for network intrusion detection. 2nd ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2006, San Jose, CA, 3 December 2006 through 5 December 2006 (pp. 183-192). (1595935800 (ISBN); 9781595935809 (ISBN)).
  190. Chrysos, N.I., & Katevenis, M.G.H. (2006). Preventing buffer-credit accumulations in switches with small, shared output queues. Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2006), Poznan, Poland, 7-9 June (pp. 8 pp.).
  191. Martinez, A., Apostolopoulos, G., Alfaro, F.J., Sanchez, J.L., & Duato, J. (2006). QoS support for video transmission in high-speed interconnects. 2nd International Conference on High Performance Computing and Communications, HPCC 2006, Munich, 13 September 2006 through 15 September 2006 (vol. 4208 LNCS, pp. 631-641). (03029743; 3540393684 (ISBN); 9783540393689 (ISBN)).
  192. Chrysos, N.I., & Katevenis, M.G.H. (2006). Scheduling in non-blocking buffered three-stage switching fabrics. INFOCOM 2006: 25th IEEE International Conference on Computer Communications, Barcelona, 23 April 2006 through 29 April 2006. (0743166X; 1424402212 (ISBN); 9781424402212 (ISBN)).
  193. Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Using lightweight transactions and snapshots for fault-tolerant services based on shared storage bricks. 2006 IEEE International Conference on Cluster Computing, Cluster 2006, Barcelona, 25 September 2006 through 28 September 2006. (15525244; 1424403286 (ISBN); 9781424403288 (ISBN)).
  194. Apostolopoulos, G., & Hassapis, C. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation. Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2006. MASCOTS 2006. 14th IEEE International Symposium on, California, USA, September 11 -13 (pp. 117-126). (1526-7539).
  195. Pnevmatikatos, D., & Arelakis, A. (2006). Variable-length hashing for exact pattern matching. 2006 International Conference on Field Programmable Logic and Applications, FPL, Madrid, 28 August 2006 through 30 August 2006 (pp. 405-410). (142440312X (ISBN); 9781424403127 (ISBN)).
  196. Papaefstathiou, V., & Papaefstathiou, I. (2005). A low-cost MAC Classification Engine. Proc. 10th Panhellenic Conference on Informatics, (PCI2005), Volos, Greece, 11-13 November.
  197. Papaefstathiou, V., & Papaefstathiou, I. (2005). A Memory Efficient, 100 Gb/sec MAC Classification Engine. LCN '05: Proceedings of the The IEEE Conference on Local Computer Networks 30th Anniversary, (pp. 470-471). Washington, DC, USA: IEEE Computer Society (0-7695-2421-4).
  198. Sourdis, I., Pnevmatikatos, D., Wang, S., & Vassiliadis, S. (2005). A reconfigurable perfect-hashing scheme for packet inspection. 2005 International Conference on Field Programmable Logic and Applications, FPL, Tampere, 24 August 2005 through 26 August 2005 (vol. 2005, pp. 644-647). (0780393627 (ISBN); 9780780393622 (ISBN)).
  199. Flourish, M.D., Anastasiadis, S.V., & Bilas, A. (2005). Block-level virtualization: How far can we go?. Local to Global Data Interoperability - Challenges and Technologies, 2005, Sardinia, 20 June 2005 through 24 June 2005 (vol. 2005, pp. 98-102). (0780392280 (ISBN); 9780780392281 (ISBN)).
  200. Zebilis, V., & Sotiriou, Ch.P. (2005). Controlling event spacing in self-timed rings. In Proceedings of the 11th IEEE International Conference on Asynchronous Circuits and Systems (ASYNC), New York, USA, 14-16 March (pp. 109). (1522-8681).
  201. Yannakopoulos, J., & Bilas, A. (2005). CORMOS: A communication-oriented runtime system for sensor networks. 2nd European Workshop onWireless Sensor Networks, EWSN 2005, Istanbul, 31 January 2005 through 2 February 2005 (vol. 2005, pp. 342-353).
  202. Papadopoulos, G., & Pnevmatikatos, D. (2005). Hashing + Memory = low cost, exact pattern matching. 2005 International Conference on Field Programmable Logic and Applications, FPL, Tampere, 24 August 2005 through 26 August 2005 (vol. 2005, pp. 39-44). (0780393627 (ISBN); 9780780393622 (ISBN)).
  203. Dimopoulos, V., Papadopoulos, G., & Pnevmatikatos, D. (2005). On the importance of header classification in HW/SW network intrusion detection systems. 10th Panhellenic Conference on Informatics, PCI 2005, Volos, Greece, 11 November 2005 through 13 November 2005 (vol. 3746 LNCS, pp. 661-671). (03029743; 3540296735 (ISBN); 9783540296737 (ISBN)).
  204. Xinidis, D., Bilas, A., & Flouris, M.D. (2005). Performance evaluation of commodity iSCSI-based storage systems. Twenty-second IEEE/Thirteenth NASA Goddard Conference on Mass Storage Systems and Technologies, IEEE/NASA MSST2005, Monterey, CA, 11 April 2005 through 14 April 2005 (pp. 261-269). (0769523188 (ISBN)).
  205. Chrysos, N.I., & Katevenis, M.G.H. (2005). Scheduling in switches with small internal buffers. GLOBECOM '05: IEEE Global Telecommunications Conference, 2005, St. Louis, MO, 28 November 2005 through 2 December 2005 (vol. 1, pp. 614-619). (0780394143 (ISBN); 9780780394148 (ISBN)).
  206. Katevenis, M.G.H., & Passas, G. (2005). Variable-size multipacket segments in buffered crossbar (CICQ) architectures. 2005 IEEE International Conference on Communications, ICC 2005, Seoul, 16 May 2005 through 20 May 2005 (vol. 2, pp. 999-1004). (05361486).
  207. Flouris, M.D., & Bilas, A. (2005). Violin: A Framework for Extensible Block-Level Storage. MSST '05: Proceedings of the 22nd IEEE / 13th NASA Goddard Conference on Mass Storage Systems and Technologies, Monterey, CA, USA, (pp. 128-142). Washington, DC, USA: IEEE Computer Society (0-7695-2318-8).
  208. Xinidis, D., Flouris, M.D., & Bilas, A. (2005). Virtual timers: Using hardware physical timers for profiling kernel code-paths. In Proc. of 8th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-8), February.
  209. Efthymiou, A., Sotiriou, Ch.P., & Edwards, D. (2004). Automatic scan insertion and pattern generation for asynchronous circuits. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, 16 February 2004 through 20 February 2004 (vol. 1, pp. 672-673). (0769520855 (ISBN)).
  210. Flouris, M.D., & Bilas, A. (2004). Clotho: Transparent data versioning at the block i/o level. In 12th NASA Goddard & 21st IEEE Conference on Mass Storage Systems and Technologies (MSST2004), April.
  211. Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2004). Coping with the variability of combinational logic delays. Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, San Jose, USA, October (pp. 505-508). (1063-6404).
  212. Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., & Sotiriou, Ch.P. (2004). From synchronous to asynchronous: An automatic approach. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, 16 February 2004 through 20 February 2004 (vol. 2, pp. 1368-1369). (0769520855 (ISBN)).
  213. Antonatos, S., Anagnostakis, K.G., & Markatos, E.P. (2004). Generating realistic workloads for network intrusion detection systems. Proceedings of the Fourth International Workshop on Software and Performance, WOSP '04, Redwood Shores, CA, 14 January 2004 through 16 January 2004 (pp. 207-215). (1581136730 (ISBN)).
  214. Cavanna, C.D., Abdelrahman, T.S., Bilas, A., & Jamieson, P. (2004). Jupiter/SVM: A JVM-based single system image for clusters of workstations. Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, 9 November 2004 through 11 November 2004 (vol. 16, pp. 121-129). (10272658).
  215. Chrysos, N.I., & Katevenis, M.G.H. (2004). Multiple priorities in a two-lane buffered crossbar. GLOBECOM '04 - IEEE Global Telecommunications Conference, Dallas, TX, 29 November 2004 through 3 December 2004 (vol. 2, pp. 1180-1186).
  216. Georgakopoulos, G.F. (2004). Nash equilibria as a fundamental issue concerning network-switches design. In Proceedings of the IEEE International Conference on Communications (ICC 2004), June (vol. 2, pp. 1080-1084).
  217. Abdelkhalek, A., & Bilas, A. (2004). Parallelization and performance of interactive multiplayer game servers. Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM), Santa Fe, NM, 26 April 2004 through 30 April 2004 (vol. 18, pp. 1017-1026). (0769521320 (ISBN); 9780769521329 (ISBN)).
  218. Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2004). Performance analysis of content matching intrusion detection systems. Proceedings - 2004 International Symposium on Applications and the Internet (Saint 2004), Tokyo, 26 January 2004 through 30 January 2004 (pp. 208-215). (0769520685 (ISBN)).
  219. Sourdis, I., & Pnevmatikatos, D. (2004). Pre-decoded CAMs for efficient and high-speed NIDS pattern matching. Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004, Napa, CA, 20 April 2004 through 23 April 2004 (pp. 258-267). (0769522300 (ISBN)).
  220. Katevenis, M.G.H., Passas, G., Simos, D.G., Papaefstathiou, I., & Chrysos, N.I. (2004). Variable packet size buffered crossbar (CICQ) switches. 2004 IEEE International Conference on Communications, Paris, 20 June 2004 through 24 June 2004 (vol. 2, pp. 1090-1096). (05361486).
  221. Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2003). A Concurrent Model for De-Synchronization. In Proceedings of the 12th International Workshop on Logic and Synthesis (IWLS), May.
  222. Sotiriou, Ch.P., & Papaefstathiou, I. (2003). A Design-Space Exploration of Alternative DES Implementations.  In Proceedings of 10th IEEE International Conference on Electronics, Circuits and Systems, (ICECS2003), United Arab Emirates, December 14 - 17. (0141-9331).
  223. Charitakis, I., Anagnostakis, K.G., & Markatos, E.P. (2003). An Active Traffic Splitter Architecture for Intrusion Detection. MASCOTS, (pp. 238-241). IEEE Computer Society (0-7695-2039-1).
  224. Amde, M., Blunno, I., & Sotiriou, Ch.P. (2003). Automating the design of an asynchronous DLX microprocessor. Proceedings of the 40th Design Automation Conference, Anaheim, CA, 2 June 2003 through 6 June 2003 (pp. 502-507). (0738100X).
  225. Sapountzis, G., & Katevenis, M.G.H. (2003). Benes Switching Fabrics with O(N)-Complexity Internal Backpressure. Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2003), tORINO, iTALY, June (pp. 11-16).
  226. Charitakis, I., Pnevmatikatos, D., Markatos, E.P., & Anagnostakis, K.G. (2003). Code generation for packet header intrusion analysis on the IXP1200 network processor. Vienna, Austria, September 24-26 (vol. 2826, pp. 226-239). (03029743).
  227. Sotiriou, Ch.P., & Lavagno, L. (2003). De-synchronization: asynchronous circuits from synchronous specifications. SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] title={De-synchronization: asynchronous circuits from synchronous specifications, Portland, Oregon, 17-20 September (pp. 165).
  228. Sotiriou, Ch.P., & Papaefstathiou, I. (2003). Design-space exploration of a cryptography algorithm. In Proceedings of the the 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), United Arab Emirates, December 2003 (vol. 2, pp. 858-861 Vol.2).
  229. Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2003). E2XB: : A Domain-Specific String Matching Algorithm for Intrusion Detection. SEC; Security and Privacy in the Age of Uncertainty, {IFIP} {TC11} 18$^th$ International Conference on Information Security ({SEC2003}), May 26-28, 2003, Athens, Greece; IFIP Conference Proceedings,, (vol. 250, pp. 217-228). Kluwer (1-4020-7449-2).
  230. Sourdis, I., & Pnevmatikatos, D. (2003). Fast, large-scale string match for a 10Gbps FPGA-based network intrusion detection system. Lisbon, Portugal, September 1-3 (vol. 2778, pp. 880-889). (03029743).
  231. Charitakis, I., Pnevmatikatos, D., Markatos, E.P., & Anagnostakis, K.G. (2003). S2I: a Tool for Automatic Rule Match Compilation for the IXP Network Processor. In Proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2003), Vienna, Austria, 24-26 September.
  232. Coppens, J., Van den Berghe, S., Bos, H., Markatos, E.P., De Turck, F., Øslebø, A., & Ubik, S. (2003). SCAMPI: A scalable and programmable architecture for monitoring gigabit networks. Workshop on End-to-End Monitoring Techniques and Services (E2EMON), Belfast, Ireland, September 7-10 (vol. 2839, pp. 475-487). (03029743).
  233. Chrysos, N.I., & Katevenis, M.G.H. (2003). Weighted fairness in buffered crossbar scheduling. Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2003), Torino, Italy, June (pp. 17-22).
  234. Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection. In Proceedings of the IASTED International Conference on Communications and Computer Networks (CCN, (pp. 146-152). ACTA Press.
  235. Sotiriou, Ch.P. (2002). Implementing asynchronous circuits using a conventional EDA tool-flow. In Proceedings of the 39th Design Automation Conference (DAC), June (pp. 415-418). (0738-100X).
  236. Papaefstathiou, I., & Sotiriou, Ch.P. (2002). Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture. WCAE '02: Proceedings of the 2002 workshop on Computer architecture education (in conjunction to the 29th International Symposium on Computer Architecture), Anchorage, Alaska, May (pp. 20). New York, NY, USA: ACM.
  237. Markatos, E.P. (2002). Speeding up TCP/IP: Faster processors are not enough. 21st IEEE International Performance, Computing, and Communications Conference, Phoenix, AZ, 3 April 2002 through 5 April 2002 (pp. 341-345).
  238. Markatos, E.P. (2002). Tracing a Large-Scale Peer to Peer System: An Hour in the Life of Gnutella. CCGRID, (pp. 65-74). IEEE Computer Society (0-7695-1582-7).
  239. Dollas, A., Pnevmatikatos, D., Aslanides, N., Kavadias, S.G., Sotiriades, E., Zogopoulos, S., Papademetriou, K., Chrysos, N.I., Harteros, K., Antonidakis, E., & Petrakis, N. (2001). Architecture and Application of PLATO, A Reconfigurable Active Network Platform. Field-Programmable Custom Computing Machines, 2001. FCCM '01. The 9th Annual IEEE Symposium on, Rohnert Park, CA, April 30 - May 2 (pp. 101-110).
  240. Sotiriou, Ch.P. (2001). Direct-mapped asynchronous finite-state machines in CMOS technology. ASIC/SOC Conference, 2001. In Proceedings of the 14th International ASIC/SOC Conference, Arlington, VA, USA, September (pp. 105-109).
  241. Gialama, E.M., Markatos, E.P., Sevaslidou, J.E., Serpanos, D.N., Kotsovinos, E.N., & Asimakopoulou, X.A. (2001). DIVISOR: Distributed video server for streaming. In Proceedings of the 5th IEEE/WSES International Conference on Circuits, Systems, Communications and Computers (CSCC 2001), July (pp. 4531-4536).
  242. Nikologiannis, A.A., & Katevenis, M.G.H. (2001). Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques. International Conference on Communications (ICC2001), Helsinki, 11 June 2000 through 14 June 2000 (vol. 7, pp. 2048-2052). (05361486).
  243. Markatos, E.P. (2001). On caching search engine query results. 5th International Web Caching and Content Delivery Workshop, 2/1 (vol. 24, pp. 137-143). (0140-3664).
  244. Tziouvaras, Ch.I., & Sartzetakis, S. (2001). Optimizing resource allocation in multi-class IP MPLS DWDM networks. In Proc. of 8th International Conference on Advances in Communications and Control (COMCON), Crete, Greece, 25-29 June.
  245. Ioannou, A., & Katevenis, M.G.H. (2001). Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. International Conference on Communications (ICC2001), Helsinki, 11 June 2000 through 14 June 2000 (vol. 7, pp. 2043-2047). (05361486).
  246. Dollas, A., Pnevmatikatos, D., Aslanides, N., Kavadias, S.G., Sotiriades, E., & Papademetriou, K. (2001). Rapid prototyping of a reusable 4×4 active ATM switch core with the PCI pamette. 12th IEEE International Workshop on Rapid System Prototyping, Monterrey, CA, 25 June 2001 through 27 June 2001 (pp. 17-23). (10746005).
  247. Pnevmatikatos, D., & Kornaros, G. (1999). ATLAS II: Optimizing a 10Gbps single-chip ATM switch. 12th Annual 1999 IEEE International ASIC/SOC Conference, Washington, DC, USA, September 15-18.
  248. Kornaros, G., Pnevmatikatos, D., Mavroidis, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Dimitriadis, G., Serpanos, D.N., & Katevenis, M.G.H. (1999). On Optimizing ATLAS I, A 10 Gbps ATM Switch. In the Proceedings of the 7-th Hellenic Conference on Informatics, Ioannina, Greece, August 26-29 (vol. IV, pp. 50-60).
  249. Markatos, E.P., Katevenis, M.G.H., Pnevmatikatos, D., & Flouris, M.D. (1999). Secondary Storage Management for Web Proxies. USENIX Symposium on Internet Technologies and Systems.
  250. Serpanos, D.N., & Wolf, W.H. (1998). Caching Web objects using Zipf"s law. October 5, 1998 (vol. 3527, pp. 320-326). SPIE.
  251. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-flow-controlled ATM for MP interconnection: The ATLAS I single-chip ATM switch. Proceedings of the 1998 4th International Symposium on High-Performance Computer Architecture, HPCA, Las Vegas, NV, USA, 31 January 1998 through 4 February 1998 (pp. 47-56). Los Alamitos, CA, United States: Institute of Electrical and Electronics Engineers Computer Society.
  252. Markatos, E.P., Tziviskou, Ch., & Papathanasiou, A E. (1998). Effective Resource Discovery on the World Wide Web. 
  253. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure. Proc. IEEE Hot Interconnects 6 Symposium, Stanford, California, USA(pp. 85-96).
  254. Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight transactions on networks of workstations. Proceedings of the 1998 18th International Conference on Distributed Computing Systems, Amsterdam, Neth, 26 May 1998 through 29 May 1998 (pp. 544-551). Piscataway, NJ, United States: IEEE.
  255. Pnevmatikatos, D., Kornaros, G., Kalokairinos, G., & Xanthaki, Ch. (1998). Memory structures of ATLAS I, a high performance, 16×16 ATM switch supporting backpressure. Proceedings of the 1998 11th Annual IEEE International ASIC Conference, Rochester, NY, USA, 13 September 1998 through 16 September 1998 (pp. 23-27). Piscataway, NJ, United States: IEEE (10630988).
  256. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction-Based Systems. In International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA '98).
  257. Papadakakis, N., Markatos, E.P., & Papathanasiou, A E. (1998). Palantir: AVisualization Tool for the World Wide Web. In Proceedings of INET '98 (The Internet Summit), Geneva, Switzerland, July.
  258. Papathanasiou, A E., Markatos, E.P., & Papadakis, S.A. (1998). PaperFinder: A Tool for Scalable Search of Digital Libraries. WebNet; Proceedings of WebNet 98 - World Conference on the {WWW} and Internet & Intranet, Orlando, Florida, {USA November 7-12, 1998, AACE (1-880094-31-2,).
  259. Pnevmatikatos, D., Kornaros, G., Kalokairinos, G., & Xanthaki, Ch. (1998). The Memory Structures of ATLAS I, a High Performance, 16x16 ATM Switch Supporting Backpressure. In Proceedings of the 11th Annual IEEE International ASIC Conference, Rochester, NY, USA, September 13-16 (pp. 23-27).
  260. Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations. CANPC, Las Vegas, Nevada, USA, January 31 - February 1 (pp. 1-14).
  261. Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS: A Single-Chip ATM Switch for NOWs. CANPC, San Antonio, Texas, USA, February 1-2 (pp. 88-101).
  262. Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed. Proceedings of HPCS '97 (4th IEEE Workshop on Arch. & Impl. of High Perf. Commun. Subsystems), Chalkidiki, Greece, June.
  263. Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-queue management and scheduling for improved QoS in communication networks. In Proceedings of the European Multimedia Microprocessor Systems and Electronic Commerce (EMMSEC '97, (pp. 906-913).
  264. Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow Control. Proceedings of ARVLSI '97 (17th Conference on Advanced Research in VLSI), MI,USA, (pp. 127-144). IEEE Computer Soc. Press (0-8186-7913-1).
  265. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching fabrics with internal backpressure using the ATLAS I single-chip ATM switch. Proceedings of the 1997 IEEE Global Telecommunications Mini-Conference, Phoenix, AZ, USA, 3 November 1997 through 8 November 1997 (vol. 1, pp. 242-246). Piscataway, NJ, United States: IEEE.
  266. Markatos, E.P., & Katevenis, M.G.H. (1997). User-level DMA without operating system kernel modification. Proceedings of the 1997 3rd International Symposium on High-Performance Computer Architecture, HPCA, San Antonio, TX, USA, 1 February 1997 through 5 February 1997 (pp. 322-331). Los Alamitos, CA, United States: IEEE.
  267. Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A general-purpose, single-chip ATM switch with credit-based flow control. Proceedings of the Hot Interconnects IV Symposium, Stanford Univ., CA, USA, August (pp. 63-73).
  268. Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure. EMSYS 96 Conference (ESPRIT OMI 6th Annual Conference: Embedded Microprocessor Systems), Berlin, Germany, September (pp. 126-136). IOS Press (90-5199-300-5).
  269. Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager. USENIX Annual Technical Conference, (pp. 177-190,).
  270. Markatos, E.P. (1996). Issues in reliable network memory paging. Proceedings of the 1996 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, San Jose, CA, USA, 1 February 1996 through 3 February 1996 (pp. 207-211). Piscataway, NJ, United States: IEEE.
  271. Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos: high-performance networking for parallel processing on workstation clusters. Proceedings of the 1996 2nd International Symposium on High-Performance Computer Architecture, HPCA, San Jose, CA, USA, 3 February 1996 through 7 February 1996 (pp. 144-153). Los Alamitos, CA, United States: IEEE.
  272. Markatos, E.P. (1996). Using remote memory to avoid disk thrashing: a simulation study. Proceedings of the 1996 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, San Jose, CA, USA, 1 February 1996 through 3 February 1996 (pp. 61-73). Piscataway, NJ, United States: IEEE.
  273. Markatos, E.P., & Dramitinos, G. (1995). Adding flexibility to a remote memory pager. Proceedings of the 4th International Workshop on Object Orientation in Operating Systems, Lund, Swed, 14 August 1995 through 15 August 1995 (pp. 183-186). Los Alamitos, CA, United States: IEEE (10635351).
  274. Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., & Serpanos, D.N. (1995). An Efficient Processor-Network Interface for Local Area Multiprocessors. Proceedings of the 4th Int. Workshop on SCI-based High-Performance Low-Cost Computing, Crete, Greece, 3 October.
  275. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches. SIGCOMM, (pp. 39-48).
  276. Vatsolaki, P., Kalokairinos, G., Stratakis, M., Xanthaki, Ch., Ligerakis, M., Kornaros, G., Dollas, A., Papadourakis, G.M., & Katevenis, M.G.H. (1995). The Implementation of Telegraphos: a High Speed Communication Architecture. In Proceedings of the 5th Panhellenic Informatics Conference, Athens Greece, December.
  277. Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch. Proceedings of the Hot Interconnects III Symposium, Stanford, California, USA, August 10-12.
  278. Ferreira, A., & Grammatikakis, M.D. (1994). Improved probabilistic routing on generalized hypercubes. In Proceedings 6th International PARLE Conference, Athens, Greece, July 4–8 (pp. 1-12).
  279. Markatos, E.P., & Chronaki, C. (1994). Using reference counters in update based coherent memory. 6th International PARLE Conference , Proceedings, Athens, Greece, July 4–8 (pp. 805-808).
  280. Grammatikakis, M.D., Hsu, D., & Hwang, F. (1993). Adaptive and oblivious algorithms for d-cube permutation routing. In Proceedings 4th International Symposium, ISAAC '93, Hong Kong, December 15–17 (pp. 167-175).
  281. Grammatikakis, M.D., & Jwo, J.S. (1993). Simulating Store-Forward Communication.. PARCO, (pp. 681-684). Elsevier (0-444-81841-3).
  282. Katevenis, M.G.H., & Tzartzanis, N (1991). Reducing the branch penalty by rearranging instructions in a double-width memory. 4th International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, USA, 8 April 1991 through 11 April 1991 (vol. 26, pp. 15-27). New York, NY, United States: Publ by ACM.
  283. Katevenis, M.G.H., & Blatt, M.G. (1986). SWITCH DESIGN FOR SOFT-CONFIGURABLE WSI SYSTEMS. (pp. 255-270).
  284. Katevenis, M.G.H., & Blatt, M.G. (1985). SWITCH DESIGN FOR SOFT-CONFIGURABLE WSI SYSTEMS. (pp. 197-219).

Papers in Proceedings (abstract reviewed)

  1. Tzenakis, G., Papatriantafyllou, A., Kesapides, J., Pratikakis , P., Vandierendonck, H., & Nikolopoulos, D.S. (2012). BDDT:: block-level dynamic dependence analysisfor deterministic task-based parallelism. Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming, PPoPP '12, New Orleans, Louisiana, USA, February 25-29 (pp. 301-302). New York, NY, USA: ACM (978-1-4503-1160-1).
  2. Zakkak, F. S., Chasapis , D., Pratikakis , P., Bilas, A., & Nikolopoulos, D.S. (2012). Inference and declaration of independence: Impact on deterministic task parallelism. Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT 2012), September 19-23 (pp. 453-454). Minneapolis.

Poster presentations (abstract reviewed)

  1. Fatourou, P., Iaremko, M., Kosmas, E., & Papadakis, G.E. (2012). Reducing contention in STM. 4th Workshop on the Theory of Transactional Memory (TransForm/EuroTM WTTM 2012), Madeira, July 2012.
  2. Chrysos, N.I., Chen, L.Y., Minkenberg, C., Kachris, C., & Katevenis, M.G.H. (2010). End-to-end congestion management for non-blocking multi-stage switching fabrics. Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS '10 , San Diego, California, USA, October 25-26.
  3. Fountoulakis, M., Marazakis, M., Flouris, M.D., & Bilas, A. (2010). A high performance commodity I/O controller for storage virtualization. Poster in the ACM/SIGOPS European Conference on Computer Systems (EuroSys 2010), Paris, France, April. New York, NY, USA: ACM.
  4. Kachris, C., Nikiforos, G., Papaefstathiou, V., Yang, X., Kavadias, S.G., & Katevenis, M.G.H. (2010). Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters. Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), IEEE International Conference on Cluster Computing (CLUSTER 2010), September 20-24.

Invited papers

  1. Fatourou, P. (2017). Concurrency for the Masses: The Paradigm of Software Transactional Memory. 19th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing (SYNASC 2017), 21-24 Sept. 2017. IEEE.
  2. Papadimitriou, K., Vatsolakis, C., & Pnevmatikatos, D. (2012). Acceleration of computationally-intensive kernels in the reconfigurable era. ReCoSoC : 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, (pp. 1-5).
  3. Tzenakis, G., Kapelonis, K., Alvanos, M., Koukos, K., Nikolopoulos, D.S., & Bilas, A. (2010). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the cell processor. 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, Pisa, January 25-27 (vol. 5952 LNCS, pp. 307-321). (03029743, 3642115144 (ISBN), 9783642115141 (ISBN)).

Tutorials

  1. Marazakis, M., Flouris, M.D., & Bilas, A. (2010). Storage Virtualization and High-Performance I/O: Storage I/O Stack Design and Implementation. Tutorial in the ACM/SIGOPS European Conference on Computer Systems, Paris, France, April (pp. 1-14). New York, NY, USA: ACM.

Edited Proceedings

  1. Fatourou, P., Jiménez, E., & Pedone, F. (2016). 20th International Conference on Principles of Distributed Systems (OPODIS'2016). Madrid, Spain, 13-16 December 2016, Madrid, Spain. (978-3-95977-031-6).
  2. Fatourou, P., & Taubenfeld, G. (2013). ACM Symposium on Principles of Distributed Computing (PODC '13). Montreal, QC, Canada, July 22 - 24, 2013. ACM.
  3. Katevenis, M.G.H., Martonosi, M., Kozyrakis, Ch., Temam, O., & Ungerer, Th. (2011). Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC'11), ACM Digital Library. Heraklion, Crete, Greece, 24-26 January (223 pages). (978-1-4503-0241-8).

Poster presentations (full-text reviewed)

  1. Mageiropoulos, E., Chrysos, N., Dimou, N., & Katevenis, M.G.H. (2021). Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices. IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2021), Orlando, FL, USA, 9-12 May (pp. 277-277). IEEE.
  2. Theodoropoulos, D., Alachiotis , N., & Pnevmatikatos, D. (2017). Multi-FPGA Evaluation Platform for Disaggregated Computing. IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017), Napa, CA, USA, 30 April-2 May (pp. 193). IEEE.
  3. Alachiotis , N., Theodoropoulos, D., & Pnevmatikatos, D. (2017). Versatile Reconfigurable Acceleration in Data Centers: a Bioinformatics Case Study. Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017), Stockholm, Sweden, January 23 (pp. 1-6).
  4. Psathakis, A., Papaefstathiou, V., Katevenis, M.G.H., & Pnevmatikatos, D. (2014). Design Trade-offs in Energy Efficient NoC Architectures. 8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2014), Ferrara, Italy, 17-19 September (pp. 186-187).
  5. Ciobanu, C.B., Pnevmatikatos, D., Papadimitriou, K., & Gaydadjiev, G.N. (2013). FASTER run-time reconfiguration management. ICS '13 Proceedings of the 27th international ACM conference on International conference on supercomputing, June 10 - 14, 2013 (pp. 463-464). Eugene, Oregon, USA: ACM.

Workshops (35)

Papers in Proceedings (full-paper reviewed)

  1. Maliaroudakis, E., Chazapis, A., Kanterakis, A., Marazakis, M., & Bilas, A. (2022). Interactive, Cloud-Native Workflows on HPC Using KNoC. Fifth International Workshop on Interactive HPC (Interactive HPC 2022) - held In conjunction with ISC22, Messe Hamburg, Germany, Jun 2.
  2. Sfakianakis, Y.S, Marazakis, M., Kozanitis, Ch., & Bilas, A. (2022). LatEst: Vertical elasticity for millisecond serverless execution. The 2nd International Workshop on Serverless To sErvE moRe at Scale, STEERS 2022 - held in conjunction with 22nd IEEE International Symposium on Cluster, Cloud and Internet Computing (CCGrid), Taormina, Italy, 16-19 May.
  3. Nikolaidis, F., Marazakis, M., & Bilas, A. (2021). IOTier: A Virtual Testbed to evaluate systems for IoT environments. 1st Workshop on Cloud-to-Things continuum: towards the convergence of IoT, Edge and Cloud Computing - (Cloud2Things 2021). Collocated with IEEE CCGrid'21., Melbourne, Australia, (pp. 676-683). IEEE.
  4. Chazapis, A., Pinto, C., Gkoufas, Y., Kozanitis, Ch., & Bilas, A. (2021). A unified storage layer for supporting distributed workflows in kubernetes. CHEOPS '21: Proceedings of the Workshop on Challenges and Opportunities of Efficient and Performant Storage Systems, April, Article No.: 1 (pp. 1-9). ACM.
  5. Attiya, H., Ben-Baruch, O., Fatourou, P., Hendler, D., & Eleftherios , K.  (2021). Brief Announcement: Tracking in Order to Recover: Detectable Recovery of Lock-Free Data Structures. 12th Annual Non-Volatile Memories Workshop, University of California, San Diego, MARCH 7-10.
  6. Vardas, I., Ploumidis, M., & Marazakis, M. (2021). Exploring the impact of node failures on the resource allocation for parallel jobs. 14th Workshop on Resiliency in High Performance Computing (Resilience) in Clusters, Clouds, and Grids, Portugal, 30 Aug.
  7. Nikolaidis, F., Chazapis, A., Marazakis, M., & Bilas, A. (2021). Frisbee: A Suite for Benchmarking Systems Recovery. Proceedings of the 1st Workshop on High Availability and Observability of Cloud Systems (HAOC '21). Collocated with EuroSys’21., 26 April . ACM.
  8. Zaourar, L., Benazouz, M., Mouhagir, A., Jebali, F., Sassolas, T., Weill, J. Ch., Falquez, C., Ho, N., Pleiter, D. , Portero, A., Suarez, E., Petrakis, P., Papaefstathiou, V., Marazakis, M., Radulovic, M., Martinez, F., Armejach, A., Casas, M., Nocua, A., & Dolbeau, R. (2021). Multilevel Simulation-Based Co-Design of Next Generation HPC Microprocessors. PMBS21: The 12th International Workshop on Performance Modeling, Benchmarking and Simulation of High-Performance Computer Systems.
  9. Gavrielatos, V., Nagarajan, V., & Fatourou, P. (2021). Towards the Synthesis of Coherence/Replication Protocols from Consistency Models via Real-Time Orderings. Proceedings of the 8th Workshop on Principles and Practice of Consistency for Distributed Data (PaPoC '21), April, Article No.: 5 (pp. 1-10).
  10. Malliotakis, J., Papagiannis, A., Marazakis, M., & Bilas, A. (2020). HugeMap: Optimizing Memory-mapped I/O with Huge Pages for Fast Storage. Proceedings of the Workshop on Challenges and Opportunities of HPC Storage Systems (CHAOSS), co-located with EuroPar’2020, Warsaw, Poland, 24-28 August .
  11. Kolokasis, I.G., Papagiannis, A., Zakkak, F. S., Pratikakis , P., & Bilas, A. (2020). Say Goodbye to Off-heap Caches! On-heap Caches Using Memory-Mapped I/O. 12th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage'20), Co-located with Usenix ATC'20, Best Presentation Award,  Boston, MA, USA, July 2020.
  12. Chaix, F., Ioannou, A., Kossifidis, N., Dimou, N., Ieronymakis, G., Marazakis, M., Papaefstathiou, V., Flouris, V., Ligerakis, M., Ailamakis, G., Vavouris, Th., Damianakis, A., Katevenis, M.G.H., & Mavroidis, I. (2019). Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping. 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2019), Denver, CO, USA, USA, (pp. 34-41). IEEE.
  13. Kalomoiris, I., Pitsis, G., Tsagkatakis, G., Ioannou, A., Kozanitis, Ch., Dollas, A., Tsakalides, P., & Katevenis, M.G.H. (2019). An Experimental Analysis of the Opportunities to Use Field Programmable Gate Array Multiprocessors for On-Board Satellite Deep Learning Classification of Spectroscopic Observations from Future ESA Space Missions. Proceedings of the European Workshop on On-Board Data Processing (OBDP), European Space Research and Technology Centre (ESTEC), Amsterdam, Netehrlands, 25-27 February 2019.
  14. Kallimanis, N., Marazakis, M., & Chrysos, N. (2019). GSAS: A Fast Shared Memory Abstraction with Minimal Hardware Support. EuroExaScale workshop on HiPEAC 2019, Valencia, Spain, 21-23 January 2019.
  15. Ploumidis, M., Kallimanis, N., Asiminakis, M., Chrysos, N., Xirouchakis, P., Gianoudis, M., Tzanakis, L., Dimou, N., Psistakis, A., Peristerakis, P., Kalokairinos, G., Papaefstathiou, V., & Katevenis, M.G.H. (2019). Software and Hardware co-design for low-power HPC platforms. High Performance Computing : ISC High Performance 2019 International Workshops, Frankfurt, Germany, June 16-20 (vol. 11887 LNCS, pp. 88-100). Springer.
  16. Papakonstantinou, N., Kallimanis, N., & Pratikakis , P. (2019). Towards Support for Recursive Task-Parallelism on ExaScale Architectures. EuroExaScale workshop on HiPEAC 2019, Valencia, Spain, 21-23 January 2019.
  17. Kallimanis, N., Chrysos, N., & Marazakis, M. (2018). A flexible & Efficient Shared Memory Abstraction with Minimal HW Assistance. EuroEXA, ExaNeSt, ExaNode, Ecoscale workshop on European HPC Summit Week, Ljubljana, Slovenia, 31 May 2018.
  18. Kallimanis, N., Marazakis, M., & Skordalakis, E. (2018). Use-cases for Remote Memory in the Unimem Architecture. ExascaleHPC workshop - HiPEAC 2018, Manchester, UK, 22 - 24 January 2018 .
  19. Papagiannis, A., Saloustros, G., Marazakis, M., & Bilas, A. (2016). User-Space I/O for μs-level Storage Devices. High Performance Computing, ISC High Performance 2016 International Workshops ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P3MA, VHPC, WOPSSS , Frankfurt, Germany, (vol. 9945 LNCS, pp. 638-648). Springer.
  20. Gonzalez-Ferez, P., & Bilas, A. (2015). NUMA impact on network storage protocolsover high-speed raw Ethernet. Proceedings of: Second International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2015), Krakow , Poland, 10-11 September (pp. 83-93).
  21. Dolev, S., Fatourou, P., & Kosmas, E. (2013). Abort Free SemanticTM by Dependency Aware Scheduling of Transactional Instructions. 5th Workshop on the Theory of Transactional Memory TransForm/EuroTM WTTM 2013 , Jerusalem, Israel, October 13.
  22. Baryannis, G., Garefalakis, P., Kritikos, K., Magoutis, K., Papaioannou, A., Plexousakis, D., & Zeginis, Ch. (2013). Lifecycle Management of Service-based Applications on Multi-Clouds: A Research Roadmap. in Proceedings of the International Workshop on Multi-cloud Applications and Federated Clouds (MultiCloud 2013). In conjunction with 4th ACM/SPEC International Conference on Performance Engineering Jointly organized by FP7-ICT projects MODAClouds, PaaSage and ARTIST, Prague, Czech Republic , 21st to 24th April 2013.
  23. Bushkov, V.B, Dziuma, D.D, Fatourou, P., & Guerraoui, R.G (2013). Snapshot Isolation Does Not Scale Either. 5th Workshop on the Theory of Transactional Memory TransForm/EuroTM WTTM 2013, Jerusalem, Israel, October 13.
  24. Ellen, F., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2013). Wait-Free Universal Constructions that ensure Timestamp-Ignoring Disjoint-Access Parallelism. 5th Workshop on the Theory of Transactional Memory TransForm/EuroTM WTTM 2013, Jerusalem, Israel, October 13.
  25. Dolev, S., Fatourou, P., & Kosmas, E. (2013). Abort Free SemanticTM by Dependency Aware Scheduling of Transactional Instructions. Proceedings of the 8th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Houston, TX, USA , March 17.
  26. Chinis, G., Pratikakis , P., Athanasopoulos, E., & Ioannidis, S. (2013). Practical Information Flow for Legacy Web Applications.  Proceedings of the 8th Workshop on Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems, ICOOOLPS'13 , Montpellier, France, July (pp. 17-28). ACM.
  27. Skarlatos, D, Pratikakis , P., & Pnevmatikatos, D. (2013). Towards Reliable Task Parallel Programs . 5th Workshop on Design for Reliability (DFR 2013) , January 21-23. Berlin, Germany.
  28. Akram, S., Marazakis, M., & Bilas, A. (2012). Energy Inefficiency of Operating System Layers for Data-centric Infrastructures. 2nd workshop on Systems for Future Multi-core Architectures (SFMA'12). In conjunction with Eurosys'12, April 2012. Bern, Switzerland.
  29. Chalkiadaki, M., & Magoutis, K. (2012). Managing Service Performance in NoSQL Distributed Storage Systems. Proceedings of the 7th Middleware for Next-Generation Internet Computing (MW4NG) Workshop of the 13th International Middleware Conference 2012, December 3-7. Montreal, Canada.
  30. Akram, S., Marazakis, M., & Bilas, A. (2012). NUMA Implications for Storage I/O Throughput in Modern Servers. 3rd Workshop on Computer Architecture and Operating System co-design (CAOS'12). In conjunction with the 7th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'12),  , January 2012. Paris, France.
  31. Pratikakis , P., Vandierendonck, H., Lyberis, S., & Nikolopoulos, D.S. (2011). A programming model for deterministic task parallelism. Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC '11, San Jose, California, (pp. 7-12). New York, NY, USA: ACM (978-1-4503-0794-9).
  32. Akram, S., & Bilas, A. (2011). A sleep-based communication mechanism to adapt processor utilization in distributed streaming systems. In 2nd Workshop on Computer Architecture and Operating System co-design (CAOS'11). In conjunction with the 6th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'11), Heraklion, Greece, January 2011.
  33. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2011). VLSI Micro-Architectures for High-Radix Crossbar Schedulers. Proc. 5th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS 2011), Pittsburgh, PA, USA, 1-4 May (8 pages). (978-1-4503-0720-8).

Papers in Proceedings (abstract reviewed)

  1. Ploumidis, M., Psistakis, A., Asiminakis, M., Xirouchakis, P., Gianioudis, M., Peristerakis, P., Chaix, F., Papaefstathiou, V., Chrysos, N., & Katevenis , M. (2018). Exploiting the ExaNeSt Communication Primitives for a High Performance MPI Library. ExascaleHPC: the ExaNoDe, ExaNeSt, EcoScale, and EuroEXA projects, in conjunction with the HiPEAC 2018 Conference, Manchester, UK, 23 January.

Key-note addresses (Talks)

  1. Katevenis, M.G.H., & Chrysos, N. (2016). Challenges and Opportunities in Exascale-Computing Interconnects. 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS 2016), held in conjunction with the HiPEAC 2016 Conference , Prague, Czech Republic, 18 January.

Books (23)

Editor

  1. Stenstrom, P., Dubois, M., Katevenis, M.G.H., Gupta, R., & Ungerer, Th. (2008). High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Goteborg, Sweden, January 27-29, 2008, Proceedings. HiPEAC; Lecture Notes in Computer Science.  Vol. 4917 Springer, (ISBN 978-3-540-77559-1).
  2. Sauveron, D., Markantonakis, C., Bilas, A., & Quisquater, J.J. (2007). Information Security Theory and Practices. Smart Cards, Mobile and Ubiquitous Computing Systems, First IFIP TC6 / WG 8.8 / WG 11.2 International Workshop, WISTP 2007, Heraklion, Crete, Greece, May 9-11, 2007, Proceedings. WISTP; Lecture Notes in Computer Science.  Vol. 4462 Springer, (ISBN 978-3-540-72353-0).
  3. Talia, D., Bilas, A., & Dikaiakos, M. (2007). Knowledge and Data Management in GRIDs.  (pp. 254), Vol. XVIII Springer, (ISBN 978-0-387-37830-5).

Chapters (in book)

  1. Pinto, C., Chazapis, A., Kozanitis, Ch., Gkoufas, Y., Koutsovasilis, P., Venugopal, S., Acquaviva, J. Th., & Bilas, A. (2021). Data Convergence for High-Performance Cloud. HPC, Big Data, AI Convergence Towards Exascale : Challenge and Vision, Chapter 9.  CRC Press, (ISBN 9781032009841).
  2. Goz, D., Ieronymakis, G., Papaefstathiou, V., Dimou, N., Bertocco, S., Ragagnin, A., Tornatore, L., Taffoni, G., & Coretti, I. (2020). Direct N-Body Application on Low-Power and Energy-Efficient Parallel Architectures. Parallel Computing: Technology Trends, Series: Advances in Parallel Computing.  Vol. 36 (pp. 583 - 592), IOS Press.
  3. Fatourou, P., & Hankin, Ch. (2019). Welcome to the Europe Region Special Section.  Vol. 62(4) (pp. p. 28), ACM.
  4. Fatourou, P., Iaremko, M., Kanellou, E.K., & Kosmas, E. (2015). Algorithmic Techniques in STM Design. Transactional Memory. Foundations, Algorithms, Tools, and Applications : COST Action Euro-TM IC1001.  Vol. 8913 (pp. 101 - 126), Springer, (ISBN 978-3-319-14719-2 (Print) 978-3-319-14720-8 (Online)).
  5. Fatourou, P., & Dziuma, D.D, Kanellou, E.K. (2015). Consistency for Transactional Memory Computing.  Transactional Memory. Foundations, Algorithms, Tools, and Applications : COST Action Euro-TM IC1001.  Vol. 8913 (pp. 3 - 31), Springer, (ISBN 978-3-319-14719-2 (Print) 978-3-319-14720-8 (Online)).
  6. Attiya, H., & Fatourou, P. (2015). Disjoint-Access Parallelism in Software Transactional Memory. Transactional Memory. Foundations, Algorithms, Tools, and Applications : COST Action Euro-TM IC1001.  Vol. 8913 (pp. 72 - 97), Springer, (ISBN 978-3-319-14719-2 (Print) 978-3-319-14720-8 (Online)).
  7. Nou, R. , Cortes, T., Mavridis, S., & Sfakianakis, Y.S, Bilas, A. (2014). Multi/many core. High performance parallel I/O, Series: Chapman & Hall/CRC Computational Science. Chapter 32 (pp. 353 - 362), CRC Press, (ISBN 9781466582347).
  8. Kavadias, S.G., Katevenis, M.G.H., & Pnevmatikatos, D. (2011). Network Interface Design for Explicit Communication in Chip Multiprocessors. Designing Network-on-Chip Architectures in the Nanoscale Era, J. Flich and D. Bertozzi (Eds.).  (pp. 325 - 351), (ISBN 978-1-4398-3710-8).
  9. Kornaros, G., Papaefstathiou, I., & Pnevmatikatos, D. (2009). Real-time Monitoring and Diagnostic Services for Networks-on-Chip. Networks-on-chips: theory and practice.  (9) Taylor & Francis Group LLC - CRC Press, (ISBN 1420079786).
  10. Luna, J., Dikaiakos, M., Gjermundrod, H., Flouris, M.D., Marazakis, M., & Bilas, A. (2009). Using the gLite middleware to implement a secure Intensive Care Grid System.  Springer.
  11. Német, Z., Flouris, M.D., Lachaize, R., & Bilas, A. (2007). Conductor: Support for Autonomous Configuration of Storage Systems.  (pp. 67 - 81).
  12. Katevenis, M.G.H. (2007). Interprocessor Communication seen as Load-Store Instruction Generalization. The Future of Computing, essays in memory of Stamatis Vassiliadis. 28 Sep. (pp. 55 - 68), Delft, The Netherlands, (ISBN 978-90-807957-3-0).
  13. Flouris, M.D., Lachaize, R., & Bilas, A. (2007). Violin: A Framework for Extensible Block-Level Storage.  (pp. 83 - 98).
  14. Danalis, A., & Markatos, E.P. (2001). Web Caching: A Survey. Enterprise Networking: Multilayer Switching and Applications. .
  15. Markatos, E.P., & Leblanc, Th.J. (1999). Multiprogramming and Multiprocessing. Wiley Encyclopedia of Electrical and Electronics Engineering. .
  16. Flouris, M.D., & Markatos, E.P. (1999). Network RA, in High Performance Cluster Computing: Architectures and Systems. High Performance Cluster Computing.  Vol. 1, Architectures and Systems (pp. 383 - 408), Upper Saddle River, NJ: Prentice Hall PTR.
  17. Markatos, E.P., & Leblanc, Th.J. (1996). Locality-Based Scheduling in Shared-Memory Multiprocessors. In Parallel Computing: Paradigms and Applications.  (8) (pp. 237 - 276), International Thomoson Computer Press, (ISBN 1-85032188-4).
  18. Katevenis, M.G.H. (1995). RISC Architectures. In Parallel and Distributed Computing Handbook.  McGraw-Hill, (ISBN 0-07-073020-).
  19. Markatos, E.P. (1994). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors. Parallel Computing: Trends and Applications, PARCO '93.  (pp. 627 - 630), Grenoble, France: Elsevier.

Edited Proceedings

  1. Gritzalis, S., Plexousakis, D., & Pnevmatikatos, D. (2009). PCI 2009, 13th Panhellenic Conference on Informatics, 10-12 September 2009, Corfu, Greece. Panhellenic Conference on Informatics.  IEEE Computer Society, (ISBN 978-0-7695-3788-7).

Periodicals (126)

Journal Articles

  1. Papagiannis, A., Saloustros, G., Xanthakis, G., Kalaentzis, G., Gonzalez-Ferez, P., & Bilas, A. (2021).  Kreon: An Efficient Memory-Mapped Key-Value Store for Flash Storage. ACM Transactions on Storage, 17(1), 1-32, ACM.
  2. Peng, B., Fatourou, P., & Palpanas, T. (2021). Fast data series indexing for in-memory data. The VLDB Journal, 30(6), 1041-1067, Springer.
  3. Peng, B., Fatourou, P., & Palpanas, T. (2021). ParIS+: Data Series Indexing on Modern Hardware. IEEE Transactions on Knowledge and Data Engineering, 33(5), 2151-2164, IEEE.
  4. Kallimanis, N. (2021). Synch: A framework for concurrent data-structures and benchmarks. Journal of Open Source Software, 6(64), 3143.
  5. Braoudaki, A., Kanellou, E.K., Kozanitis, Ch., & Fatourou, P. (2020). Hybrid Data Driven and Rule Based Sentiment Analysis on Greek Text. Procedia Computer Science, 178, 234-243, Elsevier.
  6. Goz, D., Ieronymakis, G., Papaefstathiou, V., Dimou, N., Bertocco, S., Simula, F., Ragagnin, A., Tornatore, L., & Taffoni, G. (2020). Performance and Energy Footprint Assessment of FPGAs and GPUs on HPC Systems Using Astrophysics Application. Computation, 8 (2), MDPI.
  7. Fatourou, P., & Kallimanis, N. (2020). The RedBlue family of universal constructions. Distributed Computing, 33(6), 485-513, Springer.
  8. Ioannou, A., Georgopoulos, K., Malakonakis, P., Pnevmatikatos, D., Papaefstathiou, V., Papaefstathiou, I., & Mavroidis, I. (2020). UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems. ACM Transactions on Reconfigurable Technology and Systems, 13(4), 1-32, ACM.
  9. Tsamardinos, I., Borboudakis, G., Katsogridakis , P., Pratikakis , P., & Christophides, V. (2019). A greedy feature selection algorithm for Big Data of high dimensionality. Machine Learning, 108(2), 149-202, Springer.
  10. Klimova, A., Bilas, A., Harmandaris, V., Kozanitis, Ch., Holyst, J., & Boukhanovsky, A. (2019). Computational Science by Youth: Further Steps. Procedia Computer Science, 156, 1-2, Elsevier.
  11. Papadaki, M., Sfakianakis, Y.S, Kozanitis, Ch., & Bilas, A. (2019). Syntix: A Profiling Based Resource Estimator for CUDA Kernels . Procedia Computer Science, 156, 3-12, Elsevier.
  12. Bushkov, V.B, Dziuma, D.D, Fatourou, P., & Guerraoui, R.G (2019). The PCL Theorem: Transactions cannot be Parallel, Consistent, and Live. Journal of the ACM, 66(1), Article No. 2 , ACM.
  13. Kanellou, E.K., Chrysos, N., & Bilas, A. (2018). A Flexible Datacenter Simulator. Procedia Computer Science, 136, 72-81, Elsevier.
  14. Hidri, K.K., Bilas, A., & Kozanitis, Ch. (2018). HetSpark: A Framework that Provides Heterogeneous Executors to Apache Spark. Procedia Computer Science, 136, 118-127, Elsevier.
  15. Minhas, U. I. , Russell, M., Kaloutsakis , S., Barber , P., Woods , R., Georgakoudis, G., Gillan, C., Nikolopoulos, D.S., & Bilas, A. (2018). NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams. IEEE Transactions on Multi-Scale Computing Systems , 4(3), 396-409, IEEE.
  16. Katevenis, M.G.H., Ammendola, R. , Biagioni, A., Cretaro, P., Frezza, O., Lo Cicero, F. , Lonardo, A. , Martinelli, M., Paolucci, P. S. , Pastorelli, E. , Simula, F., Vicini, P. , Taffoni, G., Pascual, J.A. , J. Navaridas, J. , Luján, M., Goodacre, J., Lietzow, B., Mouzakitis, A., Chrysos, N., Marazakis, M., Gorlani, P., Cozzini, S., Brandino, G.P., Koutsourakis, P., Ruth, J.V., Zhang, Y., & Kersten, M. (2018). Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development. Microprocessors and Microsystems, 61, 58-71, Elsevier.
  17. Sfakianakis, Y.S, Kozanitis, Ch., Kozyrakis, Ch., & Bilas, A. (2018). QuMan: Profile-based Improvement of Cluster Utilization. ACM Transactions on Architecture and Code Optimization, 15(3), 1-25, ACM.
  18. Paraskevas, K., Chrysos, N., Papaefstathiou, V., Xirouchakis, P., Peristerakis, P., Giannioudis, M., & Katevenis, M.G.H. (2018). Virtualized Multi-Channel RDMA with Software-Defined Scheduling. Procedia Computer Science, 36, 82-90, Elsevier.
  19. Antonakaki, D., Spiliotopoulos, D., Samaras, C., Pratikakis , P., Ioannidis, S., & Fragopoulou, P. (2017). Social media analysis during political turbulence. PLoS ONE , 12(10).
  20. Pavlidis , P., & Alachiotis , N. (2017). A survey of methods and tools to detect recent and strong positive selection. Journal of Biological Research-Thessaloniki, 24(7).
  21. Xu, D., Pavlidis , P., Taskent, R.O., Alachiotis , N., Flanagan, C., DeGiorgio, M., Blekhman, R., Ruhl, S., & Gokcumen, O. (2017). Archaic Hominin Introgression in Africa Contributes to Functional Salivary MUC7 Genetic Variation. Molecular Biology and Evolution, 34(10), 2704-2715.
  22. Ploumidis, M., Pappas, N., & Traganitis, A.P. (2017). Flow Allocation for Maximum Throughput and Bounded Delay on Multiple Disjoint Paths for Random Access Wireless Multihop Networks. IEEE Transactions on Vehicular Technology, 66(1), 720-733, IEEE.
  23. Fatourou, P., Nikolakopoulos, Y., & Papatriantafilou, M. (2017). Linearizable Wait-Free Iteration Operations in Shared Double-Ended Queues. Parallel Processing Letters, 27(2), World Scientific.
  24. Fatourou, P., & Kallimanis, N. (2017). Lower and upper bounds for single-scanner snapshot implementations. Distributed Computing, 30(4), 231-260, Springer .
  25. Charitopoulos, G., Koidis, L., Papadimitriou, K., & Pnevmatikatos, D. (2017). Run-time management of systems with partially reconfigurable FPGAs. Integration, the VLSI Journal, 57, 34-44, Elsevier.
  26. Theodoropoulos, D., Mazumdar, S., Ayguade, E., Bettin, N., Bueno, J., Ermini, S., Filgueras, A, Jimenez-Gonzalez, D., Alvarez-Martinez, C., Martorell, X., Montefoschi, F., Oro, D., Pnevmatikatos, D., Rizzo, A., Gai, P., Garzarella, S., Morelli, B., Pomella, A., & Giorgi , R. (2017). The AXIOM platform for next-generation cyber physical systems. Microprocessors and Microsystems, 52(July), 540-555, Elsevier.
  27. Papagiannis, A., Saloustros, G., Marazakis, M., & Bilas, A. (2016). Iris: An optimized I/O stack for low-latency storage devices. ACM SIGOPS Operating Systems Review, 50(3), 3-11, ACM.
  28. Chrysos, N., Chen, L., Kachris, C., & Katevenis , M. (2016). Discharging the Network From Its Flow Control Headaches: Packet Drops and HOL Blocking. IEEE/ACM Transactions on Networking,  24(1), 15-28, IEEE.
  29. Gonzalez-Ferez, P., & Bilas, A. (2016). Mitigation of NUMA and synchronization effects in high-speed network storage over raw Ethernet. The Journal of Supercomputing, 72(11), 4129-4159, Springer .
  30. Giorgi , R., Mazumdar, S., Viola, S., Gai, P., Garzarella, S., Morelli, B., Pnevmatikatos, D., Theodoropoulos, D., Alvarez , C., Ayguade, E., Bueno, J., Filgueras, A, Jimenez-Gonzalez, D., & Martorell, X. (2016). Modeling Multi-board Communication in the AXIOM Cyber-Physical System. Ada User Journal, 37(4), 228-235.
  31. Alvarez , C., Ayguade, E., Bosch , J., Bueno, J., Cherkashin, A., Filgueras, A, Jimenez-Gonzalez, D., Martorell, X., Navarro, N., Vidal, M., Theodoropoulos, D., Pnevmatikatos, D., Catani, D., Oro, D., Fernandez, C., Segura , C., Rodriguez Saeta, J., Hernando, J., Scordino, C., Gai, P., Passera, P., Pomella, A., Bettin, N., Rizzo, A., & Giorgi , R. (2016). The AXIOM software layers. Microprocessors and Microsystems, 47 Part B, 262-277, Elsevier.
  32. Ellen, F., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2016). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-Freedom. Distributed Computing , 29(4), 251-277, Springer.
  33. Fatourou, P., Kanellou, E.K., & Eleftherios , K. , Rabbi, M. F. (2016). WFR-TM: Wait-free readers without sacrificing speculation of writers. Journal of Parallel and Distributed Computing, 96, 134-151, Springer .
  34. Pnevmatikatos, D., Papadimitriou, K., Becker, T., Böhm , P., Brokalakis, A., Bruneel, K., Ciobanu, C.B., Davidson, T., Gaydadjiev, G., Heyse, K., Luk, W., Niu, X., Papaefstathiou, I., Pau, D., Pell, O., Pilato, C., Santambrogio, M.D., Sciuto, D., Stroobandt, D., Todman, T., & Vansteenkiste, E. (2015). FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocessors and Microsystems, 39(4-5), 321-338, Elsevier.
  35. Ploumidis, M., Pappas, N., Siris, V.A., & Traganitis, A.P. (2015). On the performance of network coding and forwarding schemes with different degrees of redundancy for wireless mesh networks. Computer Communications, 72, 49-62, Elsevier.
  36. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2015). The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches. IEEE Micro, 35(6), 38 -47, IEEE.
  37. Manousakis, I., Zakkak, F. S., Pratikakis , P., & Nikolopoulos, D.S. (2015). TProf: An energy profiler for task-parallel programs. Sustainable Computing: Informatics and Systems, 5, 1-13, Elsevier.
  38. Kitsos, I., Magoutis, K., & Tzitzikas, Y. (2014). Scalable entity-based summarization of web search results using MapReduce.  Distributed and Parallel Databases, 32(3), 405-446, Springer.
  39. Dziuma, D.D, Fatourou, P., & Kanellou, E.K. (2014). Consistency for Transactional Memory Computing. Bulletin of the EATCS , 113.
  40. Symeonidou, C., Pratikakis , P., Nikolopoulos, D.S., & Bilas, A. (2014). Distributed region-based memory allocation and synchronization. International Journal of High Performance Computing Applications, 28(4), 406-414 , ACM.
  41. Lyberis, S., Kalokairinos, G., Lygerakis , M., Papaefstathiou, V., Mavroidis, I., Katevenis, M.G.H., Pnevmatikatos, D., & Nikolopoulos, D.S. (2014). FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards. Journal of Systems Architecture (JSA), 60(6), 481-493, Elsevier.
  42. Fatourou, P., & Kallimanis, N. (2014). Highly-Efficient Wait-Free Synchronization. Theory of Computing Systems, 55(3), 475-520, Springer.
  43. Papagiannis, A., & Nikolopoulos, D.S. (2014). Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures . Journal of Systems and Software, 97, 47-64, Elsevier.
  44. Theodoropoulos, D., Kuzmanov, G., & Gaydadjiev, G. (2013). Custom architecture for multicore audio beamforming systems. ACM Transactions on Embedded Computing Systems (TECS), 13(2), No. 19 , ACM.
  45. Strydis, C., Armato , A., Bouganis, C.S., Falsafi, B., Gaydadjiev, G.N., Isaza, S., Malek, A., Mariani, R., Pnevmatikatos, D., Pradhan , D.K., Rauwerda, G., Seepers, R.M., Shafik, R.A., Sunesen, K., Theodoropoulos, D., Tzilis, S., & Vavouras, M. (2013). DeSyRe: On-demand system reliability. Microprocessors and Microsystems: Embedded Hardware Design, Special Issue on European Projects in Embedded System Design: EPESD2012, 37(8-C), 981-1001, Elsevier.
  46. Kachris, C., Nikiforos, G., Papaefstathiou, V., Kavadias, S.G., & Katevenis, M.G.H. (2013). NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. Journal of Systems Architecture (JSA), 59(1), 39-47, Elsevier.
  47. Kornaros, G., & Pnevmatikatos, D. (2013). A survey and taxonomy of on-chip monitoring of multicore systems-on-chip. ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(2), 17:1-17:38, ACM Press.
  48. Kavadias, S.G., Katevenis, M.G.H., Zampetakis, L.A., & Nikolopoulos, D.S. (2012). Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs. International Journal of Parallel Programming (IJPP), 40(6), 583-604, Springer (1573-7640).
  49. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2012). Crossbar NoCs Are Scalable Beyond 100 Nodes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 31(4), 573-585, (ISSN0278-0070).
  50. Suarez Gracia, D., Dimitrakopoulos, G., Monreal, A., Katevenis, M.G.H., & Vinals Yufera, V. (2012). LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), 20(8), 1510-1523, (1063-8210), earlier published on-line: vol. PP, no. 99, July 2011.
  51. Klonatos, Y., Makatos, A., Marazakis, M., Flouris, M.D., & Bilas, A. (2012). Transparent online storage compression at the block-level. ACM Transactions on Storage (TOS), 8(2), 5:1-5:33.
  52. Chrysos, N., & Katevenis, M.G.H. (2011). Distributed WFQ scheduling converging to weighted max-min fairness. Computer Networks: The International Journal of Computer and Telecommunications Networking , 55(3), 792-806, New York, NY, USA: Elsevier North-Holland, Inc. (ISSN 1389-1286).
  53. Attiya, H., Faith, E., & Fatourou, P. (2011). The complexity of updating snapshot objects. J. Parallel Distrib. Comput., 71(12), 1570-1577, Orlando, FL, USA: Academic Press, Inc. (ISSN 0743-7315).
  54. Ferrer, R., Bellens, P., Yeom, J.S., Schneider, Sc., Koukos, K., Alvanos, M., Beltran, V., González, M., Martorell, X., Badia, R.M., Nikolopoulos, D.S., Bilas, A., & Ayguade, E. (2010). Parallel Programming Models for Heterogeneous Multicore Architectures. IEEE Micro, 30(5), 42-53, (0272-1732).
  55. Luna, J., Dikaiakos, M., Marazakis, M., & Kyprianou, Th. (2010). Data-centric privacy protocol for intensive care grids. , 14(6), 1327-1337, (1089-7771).
  56. Katevenis, M.G.H., Papaefstathiou, V., Kavadias, S.G., Pnevmatikatos, D., Silla, F., & Nikolopoulos, D.S. (2010). Explicit Communication and Synchronization in SARC. IEEE Micro, 30(5), 30-41, (0272-1732).
  57. Flouris, M.D., Lachaize, R., Chasapis, K., & Bilas, A. (2010). Extensible block-level storage virtualization in cluster-based systems. Journal of Parallel and Distributed Computing, 70(8), 800-824, (07437315).
  58. Kalokairinos, G., Papaefstathiou, V., Nikiforos, G., Kavadias, S.G., Katevenis, M.G.H., Pnevmatikatos, D., & Yang, X. (2010). Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. Transactions on HiPEAC, 5(3), Springer Berlin Heidelberg.
  59. Chrysos, N.I., & Dimitrakopoulos, G. (2009). Practical high-throughput crossbar scheduling. IEEE Micro, 29(4), 22-35, (02721732).
  60. Schneider, Sc., Yeom, J.S., & Nikolopoulos, D.S. (2009). Programming Multiprocessors with Explicitly Managed Memory Hierarchies. Computer, 42(12), 28-34, Los Alamitos, CA, USA: IEEE Computer Society Press (0018-9162).
  61. Rafique, M.M., Rose, B., Butt, A.R., & Nikolopoulos, D.S. (2009). Supporting MapReduce on large-scale asymmetric multi-core clusters. SIGOPS Oper.Syst.Rev., 43(2), 25-34, New York, NY, USA: ACM (0163-5980).
  62. Simos, D.G., Papaefstathiou, I., & Katevenis, M.G.H. (2008). Building an FoC using large, buffered crossbar cores. IEEE Design and Test of Computers, 25(6), 538-548, (07407475).
  63. Sourdis, I., Pnevmatikatos, D., & Vassiliadis, S. (2008). Scalable multigigabit pattern matching for packet inspection. IEEE Trans Very Large Scale Integr VLSI Syst, 16(2), 156-166, (10638210).
  64. Manifavas, H., Papaefstathiou, I., & Sotiriou, Ch.P. (2007). High throughput, low power implementations for the DES family. WSEAS Trans.Comput., 6(3), 532-538, (11092750).
  65. Bosschere, K., Luk, W., Martorell, X., Navarro, N., O"Boyle, M., Pnevmatikatos, D., Ramirez, A., Sainrat, P., Seznec, A., Stenstrom, P., & Temam, O. (2007). High-Performance Embedded Architecture and Compilation Roadmap. , 4050, 5-29, Berlin / Heidelberg: Springer (978-3-540-71527-6).
  66. Ioannou, A., & Katevenis, M.G.H. (2007). Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. IEEE/ACM Transactions on Netwoking, 15(2), 450-461, (1063-6692).
  67. Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2006). Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 25(10), 1904-1921, (0278-0070).
  68. Dobkin, R., Ginosar, R., & Sotiriou, Ch.P. (2006). High rate data synchronization in GALS SoCs. IEEE Trans Very Large Scale Integr VLSI Syst, 14(10), 1063-1074, (10638210).
  69. Sapountzis, G., & Katevenis, M.G.H. (2005). Benes switching fabrics with O(N)-Complexity internal backpressure. IEEE Communications Magazine, 43(1), 88-94, (01636804).
  70. Zhou, Y., Bilas, A., Jagannathan, S., Xinidis, D., Dubnicki, C., & Li, K. (2005). VI-attached database storage. IEEE Trans Parallel Distrib Syst, 16(1), 35-50, (10459219).
  71. Dobkin, R., Ginosar, R., & Sotiriou, Ch.P. (2004). Data synchronization issues in GALS SoCs. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst., 10, 170-179, (15228681).
  72. Papaefstathiou, I., Papaefstathiou, V., & Sotiriou, Ch.P. (2004). Design-space exploration of the most widely used cryptography algorithms. Microprocessors Microsyst, 28(10), 561-571, (01419331).
  73. Blunno, I., Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., & Sotiriou, Ch.P. (2004). Handshake protocols for de-synchronization. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst., 10, 149-158, (15228681).
  74. Sotiriou, Ch.P., Ginosar, R., Stevens, K., Lavagno, L., & Heer, C. (2004). Message from the chairs. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst., 10, (15228681).
  75. Papaefstathiou, I., Perissakis, S., Orphanoudakis, T.G., Nikolaou, N.A., Kornaros, G., Zervos, N.A., Konstantoulakis, G., Pnevmatikatos, D., & Vlachos, K. (2004). PRO3: A hybrid NPU architecture. IEEE Micro, 24(5), 20-33, (02721732).
  76. Pnevmatikatos, D., Sourdis, I., & Vlachos, K. (2003). An efficient, low-cost I/O subsystem for network processors. IEEE Des Test Comput, 20(4), 56-64, (07407475).
  77. Sartzetakis, S., Tziouvaras, Ch.I., & Georgiadis, L. (2002). Adaptive routing algorithm for lambda switching networks. Optical Networks Magazine, 3, 476-487.
  78. Markatos, E.P., Papachristos, Ch., & Dramitinos, G. (2002). Web-based Infrastructure for Tourism Information Systems. Informatics and Telematics, Elsevier Science (ISSN: 0736-5853).
  79. Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2002). Web-conscious storage management for Web proxies. IEEE/ACM Transactions on Networking, 10(6), 735-748, (1063-6692).
  80. Ioannidis, S., Papathanasiou, A E., Magklis, G.I., Markatos, E.P., Pnevmatikatos, D., & Sevaslidou, J.E. (2001). On using reliable network RAM in networks of workstations. , 109-120, Commack, NY, USA: Nova Science Publishers, Inc (1-59033-113-3).
  81. Katevenis, M.G.H., Sapountzis, G., Kalyvianaki, E., Mavroidis, I., & Glykopoulos, G. (2001). Wormhole IP over (connectionless) ATM. IEEE/ACM Transactions on Networking, 9(5), 650-661, (10636692).
  82. Dramitinos, G., & Markatos, E.P. (1999). Adaptive and Reliable Paging to Remote Main Memory. J.Parallel Distrib.Comput., 58(3), 357-388, (07437315).
  83. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1999). ATLAS I: Implementing a single-chip ATM switch with backpressure. IEEE Micro, 19(1), 30-40, (02721732).
  84. Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1999). On using network RAM as a non-volatile buffer. Cluster Computing, 2(4), 295-303,.
  85. Ioannidis, S., Papathanasiou, A E., Magklis, G.I., Markatos, E.P., Pnevmatikatos, D., & Sevaslidou, J.E. (1999). On Using Reliable Network RAM in Networks of Workstations. Parallel and Distributed Computing Practices, 2(2), (1097-2803).
  86. Katevenis, M.G.H., Markatos, E.P., Vatsolaki, P., & Xanthaki, Ch. (1999). Remote Enqueue Operation on Networks of Workstations. Informatica - An International Journal of Computing and Informatics, 23(1), 29-39, (03505596).
  87. Flouris, M.D., & Markatos, E.P. (1999). The Network RamDisk: Using remote memory on heterogeneous NOWs. Cluster Computing, 2(4), 281-293.
  88. Papathanasiou, A E., Papadakakis, N., & Markatos, E.P. (1999). Visualizing Traffic on the World Wide Web. WebNet Journal: Internet Technologies, Applications & Issues, 1(2), 57-65, Charlottesville, VA: AACE (1522-192X).
  89. Markatos, E.P., & Chronaki, C. (1998). A TOP-10 approach to prefetching on Web. Proceedings of INET"98.
  90. Katevenis, M.G.H., Serpanos, D.N., & Dimitriadis, G. (1998). ATLAS I: A single-chip, gigabit ATM switch with HIC/HS links and multi-lane back-pressure. Microprocessors and Microsystems, 21(7-8), 481-490, (01419331).
  91. Nastou, P.E., Serpanos, D.N., & Maritsas, D.G. (1998). Average case analysis of searching in associative processing. J.Parallel Distrib.Comput., 54(2), 133-161, Orlando, FL, USA: Academic Press, Inc (0743-7315).
  92. Serpanos, D.N., Tantawi, A.N., & Tantawy, A.N. (1998). Credit scheduling: adaptive scheduling with dynamic service quota. Computer Communications, 21(10), 889-897, (0140-3664).
  93. Serpanos, D.N., Georgiadis, L., & Bouloutas, T. (1998). MMPacking: a load and storage balancing algorithm for distributed multimedia servers. IEEE Transactions on Circuits and Systems for Video Technology, 8(1), 13, (1051-8215).
  94. Katevenis, M.G.H., Markatos, E.P., Kalokairinos, G., & Dollas, A. (1997). Telegraphos: a substrate for high-performance computing on workstation clusters. Journal of Parallel and Distributed Computing, 43(2), 94-108, (0743-7315).
  95. Serpanos, D.N., Katevenis, M.G.H., & Spyridakis, E. (1997). ATLAS I: building block for ATM networks with credit-based flow control. , 162-167.
  96. Houstis, C.E., Kapidakis, S., Markatos, E.P., & Gelenbe, E. (1997). Execution of compute-intensive applications into parallel machines. Information Sciences, 97(1-2), 83-124, (0020-0255).
  97. Markatos, E.P. (1997). VISUALIZING WORKING SETS. Operating systems review., 31(4), 3, New York, N.Y.: ACM Special Interest Group on Operating Systems] (0163-5980).
  98. Bisdikian, C., Maruyama, K., Seidman, D.I., & Serpanos, D.N. (1996). Cable access beyond the hype: on residential broadband data services over HFC networks. IEEE Communications Magazine, 34(11), 128-135.
  99. Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-flow-controlled ATM over HIC links in the ASICCOM "ATLAS I" single-chip switch. Real-Time Magazine, 65-72.
  100. Markatos, E.P. (1996). Main memory caching of Web documents. Computer Networks and ISDN Systems, 28(7-11), 893-905, (0169-7552).
  101. Markatos, E.P., & Chronaki, C. (1994). Trace-Driven Simulation of Data-Alignment and Ohter Factors Affecting Update and Invalidate Based Coherent Memory. , 44-51,, IEEE Computer Society (0-8186-5292-6).
  102. Katevenis, M.G.H., Sidiropoulos, S., & Courcoubetis, C. (1991). Weighted round-robin cell multiplexing in a general-purpose ATM switch chip. IEEE J Sel Areas Commun, 9(8), 1265-1279, (07338716).
  103. Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broadband Networks . IEEE Journal on Selected Areas in Communications (JSAC), 5(8), 1315-1326, (07338716).

Magazine article

  1. Bilas, A., & Bitzou, Th. (2012). More data? Yes, thank you!. The Economist (Kathimerini), (97), 36.
  2. Katevenis, M.G.H. (2011). Ιδρύεται το Ευρωπαϊκό Κέντρο Αρχιτεκτονικής Υπολογιστών EuRECCA.  E&T Magazine of GSRT.
  3. Fatourou, P. (2011). ΤransForm: Θεωρητικές θεμελιώσεις των συστημάτων συγχρονισμού διεργασιών μέσω δοσοληψιών.  E&T Magazine of GSRT.
  4. Flouris, M.D., & Bilas, A. (2010). Nαυαγοί στον ωκεανό της πληροφορίας. The Economist (Kathimerini), 5(76), 46-47.

Newsletters articles

  1. Zakkak, F. S., & Pratikakis , P. (2014). JDMM: a java memory model for non-cache-coherent memory architectures. ACM SIGPLAN Notices , 49(11), 83-92, ACM.

ERCIM News

  1. Jimenez-Peris, R., Patino-Martinez, M., Magoutis, K., Bilas, A., & Brondino, I. (2012). CumuloNimbo: A High-Scalable Transaction Processing Platform as a Service. ERCIM News, 89, 34-35, April.
  2. Jimenez-Peris, R., Patino-Martinez, M., Magoutis, K., & Bilas, A. (2012). CumuloNimbo: A Highly-Scalable Transaction Processing Platform as a Service. , 89, 34-35, April.
  3. Bilas, A. (2010). IOLanes: Advancing the Scalability and Performance of I/O Subsystems in Multicore Platforms. ERCIM News, 82, 54-55, July 2010.
  4. Mangas, E., & Bilas, A. (2009). FLASH: Fine-Grained Localization in Wireless Sensor Networks. ERCIM News, 76, 42-43, January 2009.
  5. Nikolopoulos, D.S. (2009). Green Building Blocks - Software Stacks for Energy-Efficient Clusters and Data Centres. ERCIM News, 79, 13, July 2009.
  6. Nikolopoulos, D.S. (2008). Set-Top Supercomputing: Scalable Software for Scientific Simulations on GameConsoles. ERCIM News, 74, 44-45, July 2008.
  7. Luna, J., Dikaiakos, M., & Marazakis, M. (2008). Using Desktop Grids to Securely Store e-Health Data. ERCIM News, 74, 32-33, July 2008.
  8. Kapelonis, K., Karsson, S., & Bilas, A. (2006). TPC: Tagged Procedure Calls. ERCIM News, 67, 30-31, October 2006.
  9. Baltzakis, H., Bilas, A., & Trahanias, P.E. (2005). iWATCH: Intelligent Watch Based on Networked Smart Sensors and Autonomous Mobile Vehicles. ERCIM News, 63, 17-18, October 2005.
  10. Katevenis, M.G.H., & Chrysos, N.I. (2004). New Crossbar Directly Switches Variable-Size Packets. ERCIM News, 57, 58-59, April 2004.
  11. Bilas, A., & Markatos, E.P. (2003). Wearable Systems for Everyday Use. ERCIM News, 52, 15-16, January 2003.
  12. Markatos, E.P. (2001). ServerGrids: Available and Scalable Global Computing Platforms. ERCIM News, 45, April 2001.
  13. Pnevmatikatos, D. (1999). High-Performance ATM Switching: the ATLAS I Single Chip Switch. ERCIM News, 37, April 1999.
  14. Markatos, E.P., & Papathanasiou, A E. (1999). Monitoring and Displaying Traffic on the World Wide Web. ERCIM News, 37, April 1999.
  15. Markatos, E.P. (1998). TeachWEB - Novel Learning Approaches using the World-Wide Web. ERCIM News, 33, April 1998.
  16. Markatos, E.P., & Chronaki, C. (1996). Caching, Prefetching and Coherence in the World Wide Web. ERCIM News, 25, April 1996.
  17. Nikolaou, Ch., Saridakis, T., & Markatos, E.P. (1995). ArrayTracer. ERCIM News, 23, April 1995.
  18. Katevenis, M.G.H., & Georgis, Ch. (1995). The Labyrinth System. , 20, January 1995.

Talks (15)

Distinguished Lectures

  1. Fatourou, P. (2017). Concurrency for the masses: the Paradigm of Transactional Memory. South East European University, FYROM, February 23, 2017, February 23.
  2. Fatourou, P. (2017). Concurrency for the masses: the Paradigm of Transactional Memory. 19th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, Timisoara, Romania, September 21-24.
  3. Fatourou, P. (2017). Harnessing the Difficulties of Synchronization. Ss. Cyril and Methodius University - Skopje, Faculty of Computer Science and Engineering, February 24.
  4. Katevenis, M.G.H. (2008). Towards Unified Mechanisms for Inter-Processor Communication.  IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, Greece, 21-24 July.

Invited Talks

  1. Pratikakis , P. (2013). The Formic Architecture and the Myrmics Runtime System Berlin, Germany, . ENCORE & PEPPHER Workshop on Programmability and Portability for Emerging Architectures (EPoPPEA’13), January , Berlin, Germany.
  2. Pratikakis , P. (2012). Distributed Region-Based Memory Management . University of Maryland, College Park, August .
  3. Magoutis, K. (2012). Recent Advances in Large-scale IT Service Management Technologies. 6th Advanced School on Service Oriented Computing , July 2- 7, Hersonissos, Crete, Greece.
  4. Bilas, A. (2012). Scaling I/O in Virtualized Muticore Servers: How much I/O in 10 years and how to get there . Invited Talk: The 6th International Workshop on Virtualization Technologies in Distributed Computing (VTDC'12), June 19, Delft, The Netherlands, in conjunction with the 21th edition of HPDC'12 .
  5. Bilas, A. (2012). Server Storage I/O: How Much I/O and How To Get There . Intel European Research and Innovation Conference 2012 - Intel ERIC , October 22-23, Barcelona, Spain.
  6. Katevenis, M.G.H. (2012). Task Parallelism, Explicit Communication, and Architectural Support for them. Nano-Tera/Artist Summer School on Embedded System Design, Aix-les-Bains, France, 17-21 Sep..
  7. Katevenis, M.G.H. (2011). Informatics High Technology as a Tool in Medicine. Medical School Graduation Ceremony, University of Crete, Heraklion, Greece, 15 July.
  8. Katevenis, M.G.H. (2010). Replicate and Migrate Objects in the Runtime, not Cache Lines or Pages in Hardware. Barcelona Multicore Workshop 2010, Barcelona, Spain, 21-22 Oct.
  9. Katevenis, M.G.H. (2007). Interprocessor Communication seen as Load-Store Instruction Generalization. Stamatis Vassiliadis Symposium - The Future of Computing, Delft, The Netherlands, 28 Sep..
  10. Katevenis, M.G.H. (2006). Towards Light-Weight Intra-CMP Network Interfaces. Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems, Stanford, California, USA, 6-7 Dec.
  11. Katevenis, M.G.H. (1993). Parallel Computer Architecture: Shared Memory versus Message Passing. Symposium of the European Research Consortium for Informatics and Mathematics (ERCIM), Rutherford Appleton Laboratory, UK, 10-12 November.

Technical & Research Reports (250)

Miscellaneous

  1. Klonatos, Y. (2011). Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. Σχεδιασμός και Αξιολόγηση Κρυφών μνημών με Solid-State Drives (SSD)για τη βελτίωση της απόδοσης της Ε/Ε αποθήκευσης. 

ICS-FORTH Technical Reports

  1. Fatourou, P., Kosmas, E., & Chatzinikolaou, K.C. (2023). A FIRST APPROACH TOWARDS DESIGNING NUMA-AWARE CONCURRENT PRIORITY QUEUES.  (2023.TR485_NUMA-Aware_Concurrent_Priority_Queues.pdf).
  2. Fatourou, P., Palpanas, T., Kosmas, E., & Paterakis, G. (2023). FreSh: A Lock-Free Data Series Index.  (2023.TR489_FreSh_A_LockFree_Data_Series_Index.pdf).
  3. Ploumidis, M., Chaix, F., Chrysos, N., Assiminakis , A.M., Flouris, V., Kallimanis, N., Kossifidis, N., Nikoloudakis, M., Petrakis, P., Dimou, N., Gianioudis, M., Ieronymakis, G., Ioannou, A., Kalokairinos, G., Xirouchakis, P., Ailamakis, G., Damianakis, A., Ligerakis, M., Makris , M.I., Vavouris, Th., Katevenis , M., Papaefstathiou, V., Marazakis, M., & Mavroidis, I. (2023). The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack.  (2023.TR488_The_Exanest_Prototype_Efficient_HPC_ARM-based_Multi-FPGA_Rack.pdf).
  4. Fatourou, P., Kallimanis, N., & Kosmas, E. (2022). Persistent Software Combining .  (2022.TR480_Persistent_Software_Combining.pdf).
  5. Fatourou, P., Kosmas, E., Palpanas, T., & Papadospyridakis, E.P (2022). Simple Data Series Indexing Techniques for a Multi-Node Environment.  (2022.TR479.Simple_Data_Series_Techniques_Multi-Node_Environment.pdf).
  6. Ben-David, N., Blelloch, G. E., Fatourou, P., Ruppert, E., Sun, Y., & Wei, Y. (2022). Space and Time Bounded Multiversion Garbage Collection.  (2022.TR482_Space_and_Time_Bounded_Multiversion_Garbage_Collection.pdf).
  7. Eleftherios , K. , Fatourou, P. (2022). Tracking in Order to Recover:Detectable Recovery of Lock-Free Data Structures .  (2022.TR481_Detectable_Recovery_Lock-Free_Data_Structures.pdf).
  8. Vardas, I. (2020). Process Placement Optimizations and Heterogeneity Extensions to the Slurm Resource Manager.  (2020.TR477_MPI_parallel_jobs_Slurm_resource_manager_extensions.pdf).
  9. Kanellou, E.K., Chrysos, N.I., & Bilas, A. (2018). Αccelerator Deployment Models for Heterogeneous Processing Nodes and Datacenters.  (2018.TR473_Accelerator_Deployment_Models_Heterogeneous_Processing.pdf).
  10. Kolokasis, I.G., & Pratikakis , P. (2018). Cut to Fit: Tailoring the Partitioning to the Computation.  (2018.TR469_Cut_To_Fit_Partitioning_Evaluation.pdf).
  11. Fatourou, P., & Ruppert, E. (2018). Persistent Non-Blocking Binary Search Trees Supporting Wait-Free Range Queries .  (2018.TR470_Persistent_non_Blocking_Binary_Search_Trees.pdf).
  12. Zakkak, F. S. (2017). Java on Scalable Memory Architectures.  (2017.TR464_JAVA_on_Scalable_Memory_Architectures.pdf).
  13. Zakkak, F. S., & Pratikakis , P. (2016). DiSquawk: 512 cores, 512 memories, 1 JVM.  (2016.TR470_DiSquawk_512cores_512memories.pdf).
  14. Fatourou, P., Kallimanis, N., Kanellou, E.K., Makridakis, O., & Symeonidou, C. (2015). Distributed data structures for future many-core architectures.  (2015.TR447.Apr2015.pdf).
  15. Poulios, P.D. (2015). Low-Latency Implementation of Network Sockets over Remote DMA.  (2015.TR455_Low-Latency_Network_Sockets_Remote_DMA.pdf).
  16. Velegrakis, J.V. (2015). Operating System Mechanisms for Remote Resource Utilization in ARM Microservers.  (2015.TR452_Operating_System_Mechanisms_ARM_Microservers.pdf).
  17. Kallimanis, N., & Fatourou, P. (2014). The Power of Scheduling-Aware Synchronization.  (2014.TR442_Scheduling-Aware_Synchronization.pdf).
  18. Sfakianakis, Y.S, Mavridis, S., Fountoulakis, M., Papageorgiou, S.P, Chasapis, K., Papagiannis, A., Marazakis, M., & Bilas, A. (2014). Vanguard:Increasing Server Utilization via Workload Isolation in the Storage I/O Path.  (TR446_Vanguard_Increasing_Server_Utilization_Storage.pdf).
  19. Lyberis, S. (2013). Myrmics: A Scalable Runtime System for Global Address Spaces.  (2013.TR436_Myrmics_Scalable_Runtime_System_Global_Address_Spaces.pdf).
  20. Bushkov, V.B, Fatourou, P., & Dziuma, D.D, Guerraoui, R.G (2013). Snapshot Isolation Does Not Scale Either.  (2013.TR437_Snapshot_Isolation_Does_Not_Scale_Either.pdf).
  21. Dziuma, D.D, Fatourou, P., & Kanellou, E.K. (2013). Survey on consistency conditions.  (2013.TR439_Survey_on_Consistency_Conditions.pdf).
  22. Tzenakis, G., Papatriantafyllou, A., Zakkak, F. S., Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D. (2012). BDDT: Block-level Dynamic Dependence Analysis for Deterministic Task-Based Parallelism.  (2012.TR426_Block-level_Dynamic_Dependence_Analysis_for_Deterministic_Task-Based_Parallelism.pdf).
  23. Pratikakis , P., Chinis, G, Athanasopoulos, E., & Ioannidis, S. (2012). Practical Information Flow for Legacy Web Applications.  (2012.TR428_Practical-Information_Flow_for_Legacy_Web_Applications.pdf).
  24. Lyberis, S., & Kalokairinos, G. (2012). The 512-core Formic Hardware Prototype : Architecture Manual & Programmer's Model.  (2012.TR430_The_512-core_Formic_Hardware_Prototype.pdf).
  25. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars.  (2012.TR427_VLSI_Micro-Architectures_High-Radix_Crossbars.pdf).
  26. Tsaliagos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol.  (2011.TR418_Directory_based_Cache_Coherence_Protocol.pdf).
  27. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors.  (2010.TR411_Direct_Communication_Synchr_Mechanisms_Chip_Multiprocessors.pdf).
  28. Nikiforos, G. (2010). FPGA implementation of a cache controller with configurable scratchpad space.  (2010.TR402_FPGA_Cache_Controller.pdf).
  29. Mihelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes.  (2007.TR391_Approaching_Ideal_NoC_Latency.pdf).
  30. Papamichael, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors.  (2007.TR392_Network_Interface_Architecture_Chip_Cluster_Multiprocessors.pdf).
  31. Chrysos, N.I. (2007). Request-Grant Scheduling for Congestion Elimination in Multistage Networks.  (2007.TR388_Congestion_Elimination_Multistage_Networks.pdf).
  32. Apostolopoulos, G. (2006). Building Extensible and Robust Networking Systems using Virtual Machines.  (2006.TR384_Extensible_Robust_Networking_Systems.pdf).
  33. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors.  (2006.TR382_Coherent_Memory_Sub-System_Multiprocessors.pdf).
  34. Kalokairinos, G., Papaefstathiou, V., Ioannou, A., Simos, D.G., Papamichail, M., Mihelogiannakis, G., Marazakis, M., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch.  (2006.TR376_Design_Multi-Gigabit_NIC.pdf).
  35. Apostolopoulos, G., & Ciurea, I. (2006). Reducing the Forwarding State Requirements of Point-to-Multipoint Trees Using MPLS Multicast.  (2006.TR367_Reducing_Requirements_Point-to-Multipoint_Trees.pdf).
  36. Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Shared & Flexible Block I/0 for Cluster-Based Storage.  (2006.TR380_Shared_Flexible_Block_Cluster-Based_Storage.pdf).
  37. Apostolopoulos, G. (2006). Using Multiple Topologies for IP-only Protection Against Network Failures: A Routing Performance Perspective.  (2006.TR377_Routing_Performance_Perspective.pdf).
  38. Apostolopoulos, G., & Chasapis, K. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation.  (2006.TR371_V-eM_Cluster_of_Virtual_Machines.pdf).
  39. Matthaiakis, P. (2005). Study of the inter and intra die variability of the SPARTAN 2E FPGA using dual rail circuits.  (2005.TR361_Spartan_2E_FPGA_using_dual_rail_circuits.pdf).
  40. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics.  (2005.TR366.Mythical_IP_Block.pdf).
  41. Andrikos, N. (2004). Automated Flow for Digital Circuits De-synchronization.  (2004.TR338_Automated_Flow_for_Digital_Circuits_De-synchronization.pdf).
  42. Simos, D.G. (2004). Design of a 32x32 Variable-Packet-Size Buffered Crossbar Switch Chip.  (2004.TR339_Variable_Packet-Size_Buffered_Crossbar_Switch_Chip.pdf).
  43. Vlachos, E. (2004). Study of asynchronous controllers" circuits in de-synchronized systems.  (2004.TR337_Asynchronous_Controllers_Circuits.pdf).
  44. Flouris, M.D., & Bilas, A. (2004). Violin: A Framework for Extensible Block-level Storage.  (2004.TR344_Violin_Framework_Extensible_Block-level_Storage.pdf).
  45. Kokkalis, N.P. (2003). A Switching Fabric Simulator Accelerator using a systolic array of FPGA"s.  (2003.TR321.Switching_Fabric_Simulator_Accelerator_using.FPGAs.pdf).
  46. Flouris, M.D., & Bilas, A. (2003). Clotho: Transparent Data Versioning at the Block I/O Level.  (2003.TR326_Clotho_Transparent_Data_Versioning.pdf).
  47. Chrysos, N.I. (2003). Design Issues of Variable-Packet-Size, Multiple-Priority Buffered Crossbars.  (2003.TR325_Multiple-priority_Buffered_Crossbars.pdf).
  48. Passas, G. (2003). Performance Evaluation of Variable Packet Size Buffered Crossbar Switches.  (2003.TR328_Evaluation_Packet-Size_Buffered_Crossbar_Switches.pdf).
  49. Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2002). Benchmarking and Design of String Matching Intrusion Detection Systems.  (2002.TR315.benchmarking_ids.ps.gz).
  50. Sapountzis, G., & Katevenis, M.G.H. (2002). Benes Fabrics with Internal Backpressure: First Work-in-Progress Report.  (2002.TR303.Benes_Fabrics_Internal_Backpressure.ps.gz).
  51. Sapountzis, G. (2002). Benes Switching Fabrics with 0(N)-Complexity Internal Backpressure.  (2002.TR316.Bennes_Switching_Fabrics_Complexity_Internal_Backpressure.pdf.gz).
  52. Kapsalis, D. (2002). Design and implementation of a per-flow queue manager for an ATM switch using FPGA Technology.  (2002.TR302.Design_per_flow_queue_manager_FPGA_Technology.ps.gz).
  53. Sotiriou, Ch.P. (2002). Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology.  (2002.TR305.Direct-Mapped_Asynchronous_CMOS_Technology.pdf.gz).
  54. Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2002). E2 XB: A Domain-Specific String Matching Algorithm for Intrusion Detection.  (2002.TR311.Domain_String_Matching_Algorithm_Intrusion_Detection.ps.gz).
  55. Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection.  (2002.TR310.String_Matching_for_Intrusion_Detection.ps.gz).
  56. Sotiriou, Ch.P. (2002). Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow.  (2002.TR306.Asynchronous_Circuits_using_Conventional_EDA_Tool-Flow.pdf.gz).
  57. Portokalidis, G., Markatos, E.P., & Marazakis, M. (2002). Study and Bridging of Peer-to-Peer File Sharing Systems.  (2002.TR312.Bridging_Peer-to-Peer_File_Sharing_Systems.pdf.gz).
  58. Chrysos, N.I., & Katevenis, M.G.H. (2002). Weighted Max-Min Fair Scheduling for an Input-Buffered Crossbar Switch, with Small Internal Memory.  (2002.TR309.Max_Min_Fair_Scheduling_Input_Buffered_Crossbar_Switch.ps.gz).
  59. Markatos, E.P. (2001). Speeding up TCP / IP : Faster Processors are not Enough.  (2001.TR297.SpeedingUp_TCP_IP_faster_processors.ps.gz).
  60. Markatos, E.P. (2001). Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella.  (2001.TR298.Tracing_Peer_to_Peer_System.ps.gz).
  61. Ioannou, A. (2000). An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks.  (2000.TR278.ASIC_Core_Pipelined_Heap_High_Speed_Networks.ps.gz).
  62. Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2000). Web-Conscious Storage Management for Web Proxies.  (2000.TR275.Web-Conscious_Storage_Management_Web-Proxies.ps.gz).
  63. Katehakis, D.G., Chalkiadakis, G., Tsiknakis, M.N., & Orphanoudakis, S.C. (1999). A distributed, agent-based architecture for the acquisition, management, archiving and display of real-time monitoring data in the intensive care unit..  (1999.TR261.Intensive-Care_CORBA_SoftwareAgents_real-time-ICU-monitoring.ps.gz).
  64. Dollas, A., Papadimitriou, K., Mathioudakis, C., Markatos, E.P., & Katevenis, M.G.H. (1999). Experimental ATM Network Interface Performance Evaluation.  (1999.TR244.ATM_if_perf.ps.gz).
  65. Mavroidis, I. (1999). Hardware Implementation of a Routine Filter to support Wormhole IP over ATM.  (1999.TR258.RoutingFilterCore.ps.gz).
  66. Sapountzis, G. (1999). Routing Table Organization and Management in the Wormhole IP Routing Filter.  (1999.TR257.RTOrgMng.ps.gz).
  67. Markatos, E.P. (1998). A Cash-based Approach to Caching Web Documents.  (1998.TR230.cash_based_caching.ps.gz).
  68. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch.  (1998.HPCA.atlas4mp.ps.gz).
  69. Glykopoulos, G. (1998). Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip.  (1998.TR221.ATM_Cell_Buffer_using_SDRAM.ps.gz).
  70. Mavroidis, I. (1998). Heap Management in Hardware.  (1998.TR222.Heap_Management_in_Hardware.ps.gz).
  71. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure.  (1998.HOTI.atlasIimpl.ps.gz).
  72. Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight Transactions on Networks of Workstations.  (1998.ICDCS.ps.gz).
  73. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction -Based Systems.  (1998.PDTA.RVM_EXODUS.ps.gz).
  74. Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1998). On Using Network RAM as a non-volatile Buffer.  (1998.TR227.NVRAM.ps.gz).
  75. Flouris, M.D., & Markatos, E.P. (1998). The Network RamDisk : Using Remote Memory on Heterogeneous NOWs.  (1998.TR226.nrd_TR.ps.gz).
  76. Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations.  (1998.CANPC98.REQ.ps.gz).
  77. Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS I: A Single-chip ATM switch for NOWs.  (1997.CANPC97.ATLAS.ps.gz).
  78. Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed.  (1997.HPCS97.drain_cr_buf.ps.gz).
  79. Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., Magklis, G.I., Milolidakis, G., & Oikonomou, Th. (1997). Issues in the Design and Implementation of User-Level DMA.  (1997.TR182.UDMA.ps.gz).
  80. Papathanasiou, A E., & Markatos, E.P. (1997). Lightweight Transactions on Networks of Workstations.  (1997.TR209.Lightweight_Transactions_on_NOWs.ps.gz).
  81. Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-Queue Management and Scheduling for Improved QoS in Communication Networks.  (1997.EMMSEC.Muqpro.ps.gz).
  82. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1997). On using Network Memory to Improve the Performance of Transaction-Based Systems.  (1997.TR190.Remote_memory_RVM.ps.gz).
  83. Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.  (1997.ARVLSI.Pipe_MultiQueue.ps.gz).
  84. Artavanis, M. (1997). Simulation of the Shared Disks Architecture for Transaction Processing Systems.  (1997.TR211.Simulation_SharedDisks_Archit_Transaction_Processing_Systems.ps.gz).
  85. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching Fabrics with Internal Backpressure using the ATLAS I Single-Chip ATM Switch.  (1997.GLOBECOM.ATLAS_I_Fabrics.ps.gz).
  86. Markatos, E.P., & Katevenis, M.G.H. (1997). User-Level DMA without Operating System Kernel Modification.  (1997.HPCA97.user_level_dma.ps.gz).
  87. Markatos, E.P. (1997). Visualizing Working Sets.  (1997.TR192.Visualizing_working_sets.ps.gz).
  88. Markatos, E.P., & Chronaki, C. (1996). A Top-10 Approach to Prefetching on the Web.  (1996.TR173.Web_Prefetching.ps.gz).
  89. Nikolaou, Ch., Markatos, E.P., Karavassili, M., & Saridakis, T. (1996). ArrayTracer: A Parallel Performance Analysis Tool.  (1996.TR162.ArrayTracer_A_Parallel_Performance_Analysis_Tool.ps.gz).
  90. Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control.  (1996.HOTI.ATLAS_I_ATMswitchChip.ps.gz).
  91. Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure.  (1996.EMSYS96.ATLAS_I_ATMswitchHIC.ps.gz).
  92. Spyridakis, E. (1996). Comparison of Credit Based ATM and Wormhole Under Bursty Traffic or With Hot Spots.  (1996.TR170.ATM_vs_Wormhole_in_Greek.ps.gz).
  93. Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-Flow-Controlled ATM over HIC Links in the ASICCOM ''ATLAS I"" Single-Chip Switch.  (1996.RTMagazine.ATLAS_I_ATMswitchChip.ps.gz).
  94. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1996). Credit-Flow-Controlled ATM versus Wormhole Routing.  (1996.TR171.ATM_vs_Wormhole.ps.gz).
  95. Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager.  (1996.usenix.ps.gz).
  96. Markatos, E.P. (1996). Issues in Reliable Network Memory Paging.  (1996.MASCOTS96.Reliable_Network_Memory.ps.gz).
  97. Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos :High-Performance Networking for Parallel Processing on Workstation Clusters..  (1996.HPCA96.Telegraphos.ps.gz).
  98. Kozyrakis, Ch. (1996). The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch.  (1996.TR172.QueueManagement.ps.gz).
  99. Markatos, E.P. (1996). Using Remote Memory to avoid Disk Thrashing: A Simulation Study.  (1996.MASCOTS96.Remote_memory_paging.ps.gz).
  100. Efthymiou, A. (1995). Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-custom CMOS.  (1995.TR143.Design_Implementation_25Gbs_PipelinedMem_Switch_Buffer.ps.gz).
  101. Markatos, E.P., Dramitinos, G., & Papachristos, K. (1995). Implementation and Evaluation of a Remote Memory Pager.  (1995.TR129.remote_memory_paging.ps.gz).
  102. Labrinidis, A. (1995). Methods to cluster transactions into utilization classes with similar workload characteristics.  (1995.TR135.Methods_cluster_transactions_similar_workload_characteristics.ps.gz).
  103. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches.  (1995.SIGCOMM95.PipeMemoryShBuf.ps.gz).
  104. Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch.  (1995.HOTI.VCflowCtrlTeleSwitch.ps.gz).
  105. Xanthaki, Z. (1994). A Memory Controller for Access Interleaving over a single Rambus.  (1994.TR124.RAMBUS_AccessInterleaving_MemoryController.ps.gz).
  106. Chatzaki, M. (1994). A Translation Scheme Between Two Real-Time Formalisms.  (1994.TR128.specification_automatic_verification_timed_automata.ps.gz).
  107. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG Image Compression.  (1994.TR114.Arithmetic_Entropy_Codec_VLSI_chip_for_JPEG.ps.gz).
  108. Katevenis, M.G.H. (1994). FORTH, ICS: Computer Architecture and VLSI Systems Group: A Profile.  (1994.AVG_PROFILE.ps.Z).
  109. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1994). Pipelined Memory Organization for High Performance Switching and Buffering.  (1994.TR127.PipelinedMemory.ps.Z).
  110. Katevenis, M.G.H. (1994). Telegraphos: High-Speed Communication Architecture for Parallel and Distributed Computer Systems.  (1994.TR123.Telegraphos.ps.Z).
  111. Markatos, E.P., & Chronaki, C. (1994). Using reference counters in Update Based Coherent Memory.  (1994.PARLE94.Reference_Counters.ps.Z).
  112. Markatos, E.P. (1993). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors.  (1993.PARCO93.Architecture_infuence_on_Scheduling.ps.Z).
  113. Markatos, E.P., & Leblanc, Th.J. (1993). Locality-Based Scheduling in Shared-Memory Multiprocessors.  (1993.TR94.Locality_Based_Scheduling.ps.Z).
  114. Markatos, E.P., & Chronaki, C. (1993). Trace-Driven Simulation of Data-Alignment and other Factors affecting Update and Invalidate Based Coherent Memory.  (1993.TR93.DATA_ALIGNMENT_IN_VIRTUAL_SHARED_MEMORY.ps.Z).
  115. Markatos, E.P., & LeBlanc, T.J. (1993). Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors.  (1993.TPDS.Affinity_Loop_Scheduling.ps.Z).
  116. Vatsolaki, P. (1992). Design of a High-Speed UART VLSI Library Cell.  (1992.TR50.High_Speed_UART_VLSIlibCell.ps.Z).
  117. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip : Architecture and Feasibility Study.  (1991.TR025_General_Purpose_ATM_Switch_Chip.pdf).
  118. Sidiropoulos, S. (1991). Fast Packet Switches for Asynchronous Transfer Mode.  (1991.TR25.Fast_packet_switches.ps.Z).
  119. Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broad-Band Networks.  (1987.TR001_Fast-Switching_Fair-Control_Broad-Band-Networks.pdf).

M.S. Theses

  1. Kalyvianakis, G. (2022). An Efficient OpenSHMEM Implementation. 
  2. Nikoloudakis, M. (2022). Design and Implementation of a Write Based version of the Exanet MPI. 
  3. Oikonomidou, M. (2022). Multi-layer bipartite structural features to analyze YouTube Social Network. March 2022.
  4. Mousouros, O. (2022). Stream communication across RISC-V Coherence Islands, with Read-Invalidate and Write-through-Combine Cache Policies. 
  5. Xanthakis, G. (2021). Balancing Garbage Collection vs I/O Amplification using hybrid Key-Value Placement in LSM-based Key-Value Stores. July 2021.
  6. Mastorakis, I. (2021). Design and implementation of a scalable IOMMU for RISC-V architectures. July 2021.
  7. Totomis, S. (2021). Design and implementation of cache coherence engines for RISC-V systems. November 2021.
  8. Giortamis, E. (2021). Elastic resource allocation for a structural design application. July 2021.
  9. Katevenis Bitzos, G. (2021). Hierarchical shared address space MPI Collectives, for multi/many-core processors. November 2021.
  10. Vardoulakis, M. (2021). Tebis: efficient index replication for persistent LSM-based key-value stores. November 2021.
  11. Kolokasis, I.G. (2021). TeraCache: efficient Spark caching over fast storage devices. March 2021.
  12. Giaourtas, M. (2020). Design-space exploration of FPGA architectures for efficient HPC acceleration. March 2020.
  13. Kiosterakis, Ch. (2020). Efficient implementations of concurrent snapshot objects. March 2020.
  14. Kalaentzis, G. (2020). Embedding key-value stores in object and database services. November 2020.
  15. Mageiropoulos, E. (2020). Implementing convolutional neural networks in a cluster of interconnected FPGAs using Vivado HLS. November 2020.
  16. Xirouchakis, P. (2019).  Design and Implementation of the Send Part of an Advanced RDMA Engine. July 2019.
  17. Papavasileiou, E. (2019). Concurrent lock-free binary search tree implementations with range query support. July 2019.
  18. Psistakis, A. (2019). Handling of memory page faults during virtual-address RDMA. November 2019.
  19. Mikrou, S. (2019). Power and performance analysis of key-value stores on ARM and x86 based servers. November 2019.
  20. Vardas, I. (2019). Process placement optimizations and heterogeneity extensions to the Slurm resource manager. November 2019.
  21. Tzanakis Arnaoutakis, L. (2019). Quality of Service Framework for Low Power RDMA Operations over Cortex R5 Real Time Microcontroller. March 2019.
  22. Skordalakis, E. (2019). Support for different service levels through transparent migration of pages in distributed memory systems. November 2019.
  23. Batsaras, N. (2019). VAT: Asymptotic cost analysis for multi-level key-value stores. November 2019.
  24. Katsogridakis , P. (2017). Execution of Recursive Queries in Apache Spark. March 2017.
  25. Stavrakantonaki, E. (2016). A static pointer analysis on intermediate representation for compilation optimizations. 
  26. Vasilakis, E. (2015). An Instruction Level Energy Characterization of ARM Processors. 
  27. Papakonstantinou, N. (2015). Combining Recursively Parallel Runtimes with Blocked-based Dependence Analysis. 
  28. Papoulas, C. (2015). Design and Implementation of a Social Networking Architecture for Cloud Deployment Specialists. 
  29. Glenis, A. (2015). FT-Myrmics : A fault tolerant runtime system for task based programming models. 
  30. Poulios, P.D. (2015). Low-latency implementation of network sockets over remote DMA. July 2015.
  31. Velegrakis, J.V. (2015). Operating system mechanisms for remote resource utilization in ARM microservers. July 2015.
  32. Papagiannis, A. (2013). Implementing Scalable Parallel Programming Models with Hybrid Address Spaces. 
  33. Stamatakis, D. (2012). Scalability of Replicated Metadata Services in Distributed File Systems . 
  34. Chasapis, K. (2012). Bladefs: Design and Implementation of a kernel level file system for scalable storage servers. 
  35. Papatriantafyllou, A. (2012). Efficient and Accurate Block-Level Dependence Analysis For Task Dataflow Models. 
  36. Zakkak, F. S. (2012). SCOOP: Language extensions and compiler optimizations for task-based programming models. 
  37. Klonatos, I. (2011).  Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. University of Crete.
  38. Tsaliagkos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol. 
  39. Saloustros, G. (2011). Design and Implementation of a Scalable Storage System for Fully-Consistent Replicated Data Logging. 
  40. Kesapidis, I. (2011). Dynamic Dependence Analysis on Multi-core Processors. 
  41. Fountoulakis, M. (2010). DARC: Design and Evaluation of an I/O Controlller for data Protection. May 2010.
  42. Alvanos, M. (2010). Design and Evaluation of a Task -based Paraller H.264 Video Encoder for the Cell Processor. July 2010.
  43. Koukos, K. (2010). Locality management in task-based parallel programming models. August 2010.
  44. Zampetakis, M. (2010). Runtime support for programming explicit communication chip multiprocessors. July 2010.
  45. Sempepou, Z. (2010). Scalable storage support and fault-tolerance for data stream processing systems. July 2010.
  46. Katsamali, M. (2010). Software implementation of MPI primitives in multicore FPGA. June 2010.
  47. Makatos, A. (2010). ZBD: Using Transparent Compression at the Block Level to Increase Storage Space Efficiency. March 2010.
  48. Nikiforos, G. (2009). FPGA implementation of a cache controller with configurable scratchpad space. April 2009.
  49. Tzenakis, G. (2009). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the Cell Processor. November 2009.
  50. Kasapaki, E. (2008). An EDA Tool for the Timing Analysis, Optimization and Timing Validation of Asynchronous Circuits. 2008.
  51. Passas, S. (2008). Analysis and Optimization of Overheads in Communication Protocols Over High Speed Ethernet-based Cluster Interconnects. April 2008.
  52. Mangas, E. (2008). Fine-grained Localization in Wireless Sensor Networks using Acoustic Sound Transmissions and High Precision Clock Synchronization. December 2008.
  53. Aslanidis, I. (2008). Multi-valued logic synthesis. April 2008.
  54. Pantelias, E. (2008). Αποσυγχρονισμός Βιομηχανικών Κυκλωμάτων. April 2008.
  55. Michelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. September 2007.
  56. Matthaiakis, P. (2007). Gated Dual-Rail - A Methodology for Reducing the Power Consumption of Monotonic Dual-Rail Circuits. December 2007.
  57. Papamichail, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. September 2007.
  58. Andrikos, N. (2006). A Fully-Automated Desynchronization Flow for Synchronous Circuits. April 2006.
  59. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. April 2006.
  60. Kotsis, G. (2006). Improving Scalability on Shared Memory Clusters. December 2006.
  61. Passas, G. (2006). Packet Mode Scheduling in Buffered Crossbar Switches. April 2006.
  62. Panagiotakis, G. (2006). Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams. September 2006.
  63. Giannakopoulos, I. (2005). CORMOS: A Communication-Oriented Runtime System for Wireless Sensor Networks. April 2005.
  64. Papaefstathiou, V. (2005). Design and Implementation of Network Packet Classification Engines. April 2005.
  65. Dokianaki, O. (2005). Evaluation of Asynchronous Interconnect Techniques for Digital SoC. April 2005.
  66. Xynidis, D. (2005). Performance Analysis and Scaling of Networked Shared Block-Level Storage. December 2005.
  67. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. December 2005.
  68. Simos, D.G. (2004). Design of a 32x32 Variable Packet-Size Buffered Crossbar Switch Chip. November 2004.
  69. Xynidis, K. (2004). Network Intrusion Prevention on Multilevel Processing Architectures. November 2004.
  70. Sarmpanis, A. (2004). Ένα Πρωτόκολλο Εκμισθώσεων για την Ενημέρωση Δεδομένων Προσωρινών Μνημών peer-to-peer δικτύων. November 2004.
  71. Charitakis, I. (2004). Εφαρμογές του Επεξεργαστή Δικτύων IXP 1200 σε Συστήματα Ανίχνευσης Εισβολέων για Δίκτυα. April 2004.
  72. Papachristos, Ch. (2002).  Navigation Technologies over low bandwidth links for Thin Clients An introduction to the CC/PP protocol. December 2002.
  73. Kapsalis, D. (2002). Design and Implementation of a per-Flow Queue Manager of an ATM Switch using FPGA Technology. March 2002.
  74. Charteros, K. (2002). Fast Parallel Comparison Circuis for Scheduling. March 2002.
  75. MeÃntanis, D. (2002). Hardware Conversion and Software Import to a Prototype Microprocessor Board. December 2002.
  76. Kalyvianaki, E. (2002). Î§-PacketQ a network tragic visualization tool. A reial-time approach for multiple users. December 2002.
  77. Lymperis, S. (2002). Implementation of a Motion Compensaation Subsystem for an MPEG-II Decoder. December 2002.
  78. Chrysos, N. (2002). Weighted Max-Min Fair Scheduling, for a Crossbar, with Small Internal Memory. 2002.
  79. Sapountzis, G. (2002). Πλέγματα Μεταγωγής BENES με Εσωτερικό Backpressure Πολυπλοκότητας O(N). December 2002.
  80. Papadakis, G. (2001). Design and FPGA Implementation of an ABR traffic scheduler and utopia interfaces for an ATM network switch. November 2001.
  81. Gialama, A. (2001). Distributed Video Server with Quality of Service. June 2001.
  82. Asimakopoulou, X.A. (2001). Effective Resource Discovery on the World Wide Web. June 2001.
  83. Danalis, A. (2001). Firewall development for the embedded network processor IXP1200. July 2001 .
  84. Lolas, Ch. (2001). Low Level Software Design and Implementation for High Performance Packet Switches. November 2001.
  85. Ioannou, A. (2000). An ASIC Core for Pipelining Heap Management to Support Scheduling in High Speed Networks. November 2000.
  86. Oikonomou, A. (2000). Architecture and Implementation of an Adaptation Bridge for ATM Networks. June 2000.
  87. Flouris, M.D. (2000). Design & Implementation of Methods Enchancing the Performance of www Proxies. March 2000.
  88. Nikologiannis, A. (2000). Efficient Per-Flow Queuing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques. November 2000.
  89. Sidiropoulos, A. (1999). Distributed Indexing and Searching Mechanisms. March 1999.
  90. Chatzistamatiou, A. (1999). EasyAgent: a Masif Compliant Environment for Mobile Java Objects. March 1999.
  91. Papathanasiou, A E. (1999). Effective Resource Discovery on the World Wide Web. June 1999.
  92. Milolidakis, G. (1999). MemSpyer: A Performance Debugging Tool which simulates and visualizes memory hierarchy. March 1999.
  93. Glykopoulos, G. (1998). Design and Ιmplementation of an 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. July 1998.
  94. Karakonstantis, P. (1998). Efficient Memory Management for high-speed ATM networks. November 1998.
  95. Kornaros, G. (1997).  Implementation of Pipelined Multi- Queue Management in the ATLAS I Switch in Full- Custom CMOS VLSI. June 1997.
  96. Zarras, A. (1997). Array Tracer : Parallel Performance Analysis and Visualization. March 1997.
  97. Gkanas, L. (1997). New Caching ways in the World Wide Web. 1997.
  98. Terzis, S. (1997). Performance Monitoring in Digital Library Systems. November 1997.
  99. Artavanis, M. (1997). Simulation of the Shared Discks Architecture for Transaction Processing Systems. November 1997.
  100. Moraiti, M. (1997). Trace-driven Simulation of ATM and Wormhole networks. November 1997.
  101. Anastasiadi, A. (1996).  A study of Microeconomic Algorithms for Load Balancing and Data Replication in Distributed Computer Systems. November 1996.
  102. Spyridakis, E. (1996). Comparative Study of Credit Flow Controled ATM and Wormhole Networks Under Bursty Traffic and Witg Hot Spots. 1996.
  103. Papachristos, K. (1996). Design and Implementation of the Telegraphos Operations for the Mach Operating System. March 1996.
  104. Dramitinos, G. (1996). Reliable Paging to Remote Main Memory in a Workstation Cluster. 1996.
  105. Ioannidis, S. (1996). Using the Remote Main Memory in a Workstation Cluster for Reliability and Performance in Transactional Based Systems. November 1996.
  106. Sareidakis, T. (1995). Array Tracer: A Parallel Performance Analysis Tool. November 1995.
  107. Efthymiou, A. (1995). Design of a 25 Gbits/sec Pipelined Menory for Shared Buffer Network Switches. November 1995.
  108. Marazakis, M. (1995). Simulation and Transaction Processing Systems and A Study of Methods for Performance Goal Satisfaction. November 1995.
  109. Lamprinidis, A. (1995). Μέθοδοι Ταξινόμησης Δοσοληψιών σε Ομάδες με Παρόμοια Χαρακτηριστικά Φόρτου Εργασίας. November 1995.
  110. Karavasili, M. (1994). An Algorithm to Layout Directed Graphs. March 1994.
  111. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG compression. March 1994.
  112. Xanthaki, Z. (1994). Ενας Ελεγκτής για Διαφύλλωση Προσπελάσεων σε ένα Απλό Rambus. March 1994.
  113. Farsaris, I. (1993). Design and Implementation of undo-redo mechanism in Labyrinth System. May 1993.
  114. Karydis, N. (1993). Βιβλιοθήκη Γεωμετρικών Κυττάρων και Μετασχηματισμών για τον Λαβύρινθο. April 1993.
  115. Moshovos, A. (1992). Implementing Non-Numerical Algorithms On A Decoupled Architecture Supporting Software Pipelining.  (pdf in english) (pdf in greek) (slides).
  116. Kalogerakis, P. (1992). Ο Μηχανισμός Υπολογισμού Κυττάρων στο Λαβύρινθο. September 1992.
  117. Sorilos, A. (1992). Οντοκεντρικός Σχεδιασμός Γραφικών στο Σύστημα Λαβύρινθος. September 1992.
  118. Vatsolaki, P. (1992). Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI. 1992.
  119. Georgis, Ch. (1992). Σχεδιασμός και Υλοποίηση του Γραφικού Τμήματος του Λαβυρίνθου. March 1992.
  120. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip: Architecture and Feasibility Study. September 1991.
  121. Tzartzanis, N. (1991). Αναδιάταξη Κώδικα σε Μνήμη Διπλού Πλάτους για Ελάττωση του Κόστους των Διακλαδώσεων. June 1991.
  122. Chalkiadakis, V. (1990). Αρχική Σχεδίαση και Υλοποίηση του Ring 64: Δίκτυο Τοπολογίας Δακτυλίου για Πακέτα Δεδομένων και Φωνής με Ταχύτητα Μεγαλύτερη από 64 Mb/s. December 1990.

Ph.D. Theses

  1. Papagiannis, A.P (2021). Memory-mapped I/O for fast storage. March 2021.
  2. Zakkak, F. S. (2017). Java™ on Scalable Memory Architectures. March 2017.
  3. Lyberis, S. (2013). Myrmics: a scalable runtime system for global address spaces. 
  4. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars. 
  5. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors. 
  6. Chrysos, N. (2007). Request- Grant Scheduling for Congestion Elimination in Multistage Networks. May 2007.
  7. Marazakis, E. (2000). Service Composition and Service- level Agreements in Open Distributed Systems. December 2000.

Other Technical Reports

  1. Faith, E., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2012). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-Freedom. 

Other (13)

White Papers

  1. Kolokasis, I.G., Evdorou, G., Papagiannis, A.P, Zakkak, F. S., Kozanitis, Ch., Akram, S., Pratikakis , P., & Bilas, A. (2021). Freeing Compute Caches from Serialization and Garbage Collection in Managed Big Data Analytics. 
  2. Nikolaidis, F., Chazapis, A., Marazakis, M., & Bilas, A. (2021). Frisbee: automated testing of Cloud-native applications in Kubernetes. 
  3. Peng, B., Fatourou, P., & Palpanas, T. (2020). ParIS+: Data Series Indexing on Multi-Core Architectures. 
  4. Mikrou, S., Papagiannis, A.P, Saloustros, G., Marazakis, M., & Bilas, A. (2020). Power and Performance Analysis of Persistent Key-Value Stores. 
  5. Batsaras, N., Saloustros, G., Papagiannis, A.P, Fatourou, P., & Bilas, A. (2020). VAT: Asymptotic Cost Analysis for Multi-Level Key-Value Stores. 
  6. Taffoni, G., Murante, G., Tornatore, L., Goz, D., Borgani, S., Katevenis, M.G.H., Chrysos, N., & Marazakis, M. (2019). Shall numerical astrophysics step into the era of Exascale computing?. 
  7. Fatourou, P., Papageorgiou, Y., & Petousi, V. (2019). Women are needed in STEM: European policies and incentives. Communications of the ACM, ACM, 62 (4), (pp. 52-57).

Miscellaneous

  1. Chaix, F., & Fujiwara, I. , Koibuchi, M.  (2015). Evaluation of applications performance for different supercomputers network topologies. Poster presentation and short paper at the ACACES Summer School (HiPEAC). Fiuggi, Italy, July .
  2. Hessel, F., Kent, K.B., & Pnevmatikatos, D. (2008). Editorial: Embedded systems - new challenges and future directions. ACM Trans.Embedded Comput.Syst., 7 (4).

Other

  1. Braoudaki, A., Kanellou, E.K., Kozanitis, Ch., & Fatourou, P. (2021). Hybrid Data-Driven and Rule-Based Sentiment Analysis on Greek Text. 3rd Summit on Gender Equality in Computing (GEC’21. 2 July.
  2. Vardas, I., Ploumidis, M., & Marazakis, M. (2020). Improving the Performance and Resilience of MPI Parallel Jobs with Topology and Fault-Aware Process Placement. 
  3. Fatourou, P., & Pedone, F. (2020). Preface. Theoretical Computer Science, 826-827, (pp. 1).
  4. Fatourou, P., Kallimanis, N., & Kanellou, E.K. (2019). Porting Distributed Data Structures to Future Many-core Architectures. 1st Summit on Gender Equality in Computing (GEC’19). Athens, Greece, 7 June 2019.
Found: 764 publications