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FORTH - INSTITUTE OF COMPUTER SCIENCE
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Publications

Publications of Computer Architecture and VLSI Systems Laboratory (CARV)

Technical & Research Reports (249)

Miscellaneous

  1. Klonatos, Y. (2011). Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. Σχεδιασμός και Αξιολόγηση Κρυφών μνημών με Solid-State Drives (SSD)για τη βελτίωση της απόδοσης της Ε/Ε αποθήκευσης. 

ICS-FORTH Technical Reports

  1. Fatourou, P., Kosmas, E., & Chatzinikolaou, K.C. (2023). A FIRST APPROACH TOWARDS DESIGNING NUMA-AWARE CONCURRENT PRIORITY QUEUES.  (2023.TR485_NUMA-Aware_Concurrent_Priority_Queues.pdf).
  2. Ploumidis, M., Chaix, F., Chrysos, N., Assiminakis , A.M., Flouris, V., Kallimanis, N., Kossifidis, N., Nikoloudakis, M., Petrakis, P., Dimou, N., Gianioudis, M., Ieronymakis, G., Ioannou, A., Kalokairinos, G., Xirouchakis, P., Ailamakis, G., Damianakis, A., Ligerakis, M., Makris , M.I., Vavouris, Th., Katevenis , M., Papaefstathiou, V., Marazakis, M., & Mavroidis, I. (2023). The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack.  (2023.TR488_The_Exanest_Prototype_Efficient_HPC_ARM-based_Multi-FPGA_Rack.pdf).
  3. Fatourou, P., Kallimanis, N., & Kosmas, E. (2022). Persistent Software Combining .  (2022.TR480_Persistent_Software_Combining.pdf).
  4. Fatourou, P., Kosmas, E., Palpanas, T., & Papadospyridakis, E.P (2022). Simple Data Series Indexing Techniques for a Multi-Node Environment.  (2022.TR479.Simple_Data_Series_Techniques_Multi-Node_Environment.pdf).
  5. Ben-David, N., Blelloch, G. E., Fatourou, P., Ruppert, E., Sun, Y., & Wei, Y. (2022). Space and Time Bounded Multiversion Garbage Collection.  (2022.TR482_Space_and_Time_Bounded_Multiversion_Garbage_Collection.pdf).
  6. Eleftherios , K. , Fatourou, P. (2022). Tracking in Order to Recover:Detectable Recovery of Lock-Free Data Structures .  (2022.TR481_Detectable_Recovery_Lock-Free_Data_Structures.pdf).
  7. Vardas, I. (2020). Process Placement Optimizations and Heterogeneity Extensions to the Slurm Resource Manager.  (2020.TR477_MPI_parallel_jobs_Slurm_resource_manager_extensions.pdf).
  8. Kanellou, E.K., Chrysos, N.I., & Bilas, A. (2018). Αccelerator Deployment Models for Heterogeneous Processing Nodes and Datacenters.  (2018.TR473_Accelerator_Deployment_Models_Heterogeneous_Processing.pdf).
  9. Kolokasis, I.G., & Pratikakis , P. (2018). Cut to Fit: Tailoring the Partitioning to the Computation.  (2018.TR469_Cut_To_Fit_Partitioning_Evaluation.pdf).
  10. Fatourou, P., & Ruppert, E. (2018). Persistent Non-Blocking Binary Search Trees Supporting Wait-Free Range Queries .  (2018.TR470_Persistent_non_Blocking_Binary_Search_Trees.pdf).
  11. Zakkak, F. S. (2017). Java on Scalable Memory Architectures.  (2017.TR464_JAVA_on_Scalable_Memory_Architectures.pdf).
  12. Zakkak, F. S., & Pratikakis , P. (2016). DiSquawk: 512 cores, 512 memories, 1 JVM.  (2016.TR470_DiSquawk_512cores_512memories.pdf).
  13. Fatourou, P., Kallimanis, N., Kanellou, E.K., Makridakis, O., & Symeonidou, C. (2015). Distributed data structures for future many-core architectures.  (2015.TR447.Apr2015.pdf).
  14. Poulios, P.D. (2015). Low-Latency Implementation of Network Sockets over Remote DMA.  (2015.TR455_Low-Latency_Network_Sockets_Remote_DMA.pdf).
  15. Velegrakis, J.V. (2015). Operating System Mechanisms for Remote Resource Utilization in ARM Microservers.  (2015.TR452_Operating_System_Mechanisms_ARM_Microservers.pdf).
  16. Kallimanis, N., & Fatourou, P. (2014). The Power of Scheduling-Aware Synchronization.  (2014.TR442_Scheduling-Aware_Synchronization.pdf).
  17. Sfakianakis, Y.S, Mavridis, S., Fountoulakis, M., Papageorgiou, S.P, Chasapis, K., Papagiannis, A., Marazakis, M., & Bilas, A. (2014). Vanguard:Increasing Server Utilization via Workload Isolation in the Storage I/O Path.  (TR446_Vanguard_Increasing_Server_Utilization_Storage.pdf).
  18. Lyberis, S. (2013). Myrmics: A Scalable Runtime System for Global Address Spaces.  (2013.TR436_Myrmics_Scalable_Runtime_System_Global_Address_Spaces.pdf).
  19. Bushkov, V.B, Fatourou, P., & Dziuma, D.D, Guerraoui, R.G (2013). Snapshot Isolation Does Not Scale Either.  (2013.TR437_Snapshot_Isolation_Does_Not_Scale_Either.pdf).
  20. Dziuma, D.D, Fatourou, P., & Kanellou, E.K. (2013). Survey on consistency conditions.  (2013.TR439_Survey_on_Consistency_Conditions.pdf).
  21. Tzenakis, G., Papatriantafyllou, A., Zakkak, F. S., Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D. (2012). BDDT: Block-level Dynamic Dependence Analysis for Deterministic Task-Based Parallelism.  (2012.TR426_Block-level_Dynamic_Dependence_Analysis_for_Deterministic_Task-Based_Parallelism.pdf).
  22. Pratikakis , P., Chinis, G, Athanasopoulos, E., & Ioannidis, S. (2012). Practical Information Flow for Legacy Web Applications.  (2012.TR428_Practical-Information_Flow_for_Legacy_Web_Applications.pdf).
  23. Lyberis, S., & Kalokairinos, G. (2012). The 512-core Formic Hardware Prototype : Architecture Manual & Programmer's Model.  (2012.TR430_The_512-core_Formic_Hardware_Prototype.pdf).
  24. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars.  (2012.TR427_VLSI_Micro-Architectures_High-Radix_Crossbars.pdf).
  25. Tsaliagos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol.  (2011.TR418_Directory_based_Cache_Coherence_Protocol.pdf).
  26. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors.  (2010.TR411_Direct_Communication_Synchr_Mechanisms_Chip_Multiprocessors.pdf).
  27. Nikiforos, G. (2010). FPGA implementation of a cache controller with configurable scratchpad space.  (2010.TR402_FPGA_Cache_Controller.pdf).
  28. Mihelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes.  (2007.TR391_Approaching_Ideal_NoC_Latency.pdf).
  29. Papamichael, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors.  (2007.TR392_Network_Interface_Architecture_Chip_Cluster_Multiprocessors.pdf).
  30. Chrysos, N.I. (2007). Request-Grant Scheduling for Congestion Elimination in Multistage Networks.  (2007.TR388_Congestion_Elimination_Multistage_Networks.pdf).
  31. Apostolopoulos, G. (2006). Building Extensible and Robust Networking Systems using Virtual Machines.  (2006.TR384_Extensible_Robust_Networking_Systems.pdf).
  32. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors.  (2006.TR382_Coherent_Memory_Sub-System_Multiprocessors.pdf).
  33. Kalokairinos, G., Papaefstathiou, V., Ioannou, A., Simos, D.G., Papamichail, M., Mihelogiannakis, G., Marazakis, M., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch.  (2006.TR376_Design_Multi-Gigabit_NIC.pdf).
  34. Apostolopoulos, G., & Ciurea, I. (2006). Reducing the Forwarding State Requirements of Point-to-Multipoint Trees Using MPLS Multicast.  (2006.TR367_Reducing_Requirements_Point-to-Multipoint_Trees.pdf).
  35. Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Shared & Flexible Block I/0 for Cluster-Based Storage.  (2006.TR380_Shared_Flexible_Block_Cluster-Based_Storage.pdf).
  36. Apostolopoulos, G. (2006). Using Multiple Topologies for IP-only Protection Against Network Failures: A Routing Performance Perspective.  (2006.TR377_Routing_Performance_Perspective.pdf).
  37. Apostolopoulos, G., & Chasapis, K. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation.  (2006.TR371_V-eM_Cluster_of_Virtual_Machines.pdf).
  38. Matthaiakis, P. (2005). Study of the inter and intra die variability of the SPARTAN 2E FPGA using dual rail circuits.  (2005.TR361_Spartan_2E_FPGA_using_dual_rail_circuits.pdf).
  39. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics.  (2005.TR366.Mythical_IP_Block.pdf).
  40. Andrikos, N. (2004). Automated Flow for Digital Circuits De-synchronization.  (2004.TR338_Automated_Flow_for_Digital_Circuits_De-synchronization.pdf).
  41. Simos, D.G. (2004). Design of a 32x32 Variable-Packet-Size Buffered Crossbar Switch Chip.  (2004.TR339_Variable_Packet-Size_Buffered_Crossbar_Switch_Chip.pdf).
  42. Vlachos, E. (2004). Study of asynchronous controllers" circuits in de-synchronized systems.  (2004.TR337_Asynchronous_Controllers_Circuits.pdf).
  43. Flouris, M.D., & Bilas, A. (2004). Violin: A Framework for Extensible Block-level Storage.  (2004.TR344_Violin_Framework_Extensible_Block-level_Storage.pdf).
  44. Kokkalis, N.P. (2003). A Switching Fabric Simulator Accelerator using a systolic array of FPGA"s.  (2003.TR321.Switching_Fabric_Simulator_Accelerator_using.FPGAs.pdf).
  45. Flouris, M.D., & Bilas, A. (2003). Clotho: Transparent Data Versioning at the Block I/O Level.  (2003.TR326_Clotho_Transparent_Data_Versioning.pdf).
  46. Chrysos, N.I. (2003). Design Issues of Variable-Packet-Size, Multiple-Priority Buffered Crossbars.  (2003.TR325_Multiple-priority_Buffered_Crossbars.pdf).
  47. Passas, G. (2003). Performance Evaluation of Variable Packet Size Buffered Crossbar Switches.  (2003.TR328_Evaluation_Packet-Size_Buffered_Crossbar_Switches.pdf).
  48. Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2002). Benchmarking and Design of String Matching Intrusion Detection Systems.  (2002.TR315.benchmarking_ids.ps.gz).
  49. Sapountzis, G., & Katevenis, M.G.H. (2002). Benes Fabrics with Internal Backpressure: First Work-in-Progress Report.  (2002.TR303.Benes_Fabrics_Internal_Backpressure.ps.gz).
  50. Sapountzis, G. (2002). Benes Switching Fabrics with 0(N)-Complexity Internal Backpressure.  (2002.TR316.Bennes_Switching_Fabrics_Complexity_Internal_Backpressure.pdf.gz).
  51. Kapsalis, D. (2002). Design and implementation of a per-flow queue manager for an ATM switch using FPGA Technology.  (2002.TR302.Design_per_flow_queue_manager_FPGA_Technology.ps.gz).
  52. Sotiriou, Ch.P. (2002). Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology.  (2002.TR305.Direct-Mapped_Asynchronous_CMOS_Technology.pdf.gz).
  53. Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2002). E2 XB: A Domain-Specific String Matching Algorithm for Intrusion Detection.  (2002.TR311.Domain_String_Matching_Algorithm_Intrusion_Detection.ps.gz).
  54. Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection.  (2002.TR310.String_Matching_for_Intrusion_Detection.ps.gz).
  55. Sotiriou, Ch.P. (2002). Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow.  (2002.TR306.Asynchronous_Circuits_using_Conventional_EDA_Tool-Flow.pdf.gz).
  56. Portokalidis, G., Markatos, E.P., & Marazakis, M. (2002). Study and Bridging of Peer-to-Peer File Sharing Systems.  (2002.TR312.Bridging_Peer-to-Peer_File_Sharing_Systems.pdf.gz).
  57. Chrysos, N.I., & Katevenis, M.G.H. (2002). Weighted Max-Min Fair Scheduling for an Input-Buffered Crossbar Switch, with Small Internal Memory.  (2002.TR309.Max_Min_Fair_Scheduling_Input_Buffered_Crossbar_Switch.ps.gz).
  58. Markatos, E.P. (2001). Speeding up TCP / IP : Faster Processors are not Enough.  (2001.TR297.SpeedingUp_TCP_IP_faster_processors.ps.gz).
  59. Markatos, E.P. (2001). Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella.  (2001.TR298.Tracing_Peer_to_Peer_System.ps.gz).
  60. Ioannou, A. (2000). An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks.  (2000.TR278.ASIC_Core_Pipelined_Heap_High_Speed_Networks.ps.gz).
  61. Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2000). Web-Conscious Storage Management for Web Proxies.  (2000.TR275.Web-Conscious_Storage_Management_Web-Proxies.ps.gz).
  62. Katehakis, D.G., Chalkiadakis, G., Tsiknakis, M.N., & Orphanoudakis, S.C. (1999). A distributed, agent-based architecture for the acquisition, management, archiving and display of real-time monitoring data in the intensive care unit..  (1999.TR261.Intensive-Care_CORBA_SoftwareAgents_real-time-ICU-monitoring.ps.gz).
  63. Dollas, A., Papadimitriou, K., Mathioudakis, C., Markatos, E.P., & Katevenis, M.G.H. (1999). Experimental ATM Network Interface Performance Evaluation.  (1999.TR244.ATM_if_perf.ps.gz).
  64. Mavroidis, I. (1999). Hardware Implementation of a Routine Filter to support Wormhole IP over ATM.  (1999.TR258.RoutingFilterCore.ps.gz).
  65. Sapountzis, G. (1999). Routing Table Organization and Management in the Wormhole IP Routing Filter.  (1999.TR257.RTOrgMng.ps.gz).
  66. Markatos, E.P. (1998). A Cash-based Approach to Caching Web Documents.  (1998.TR230.cash_based_caching.ps.gz).
  67. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch.  (1998.HPCA.atlas4mp.ps.gz).
  68. Glykopoulos, G. (1998). Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip.  (1998.TR221.ATM_Cell_Buffer_using_SDRAM.ps.gz).
  69. Mavroidis, I. (1998). Heap Management in Hardware.  (1998.TR222.Heap_Management_in_Hardware.ps.gz).
  70. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure.  (1998.HOTI.atlasIimpl.ps.gz).
  71. Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight Transactions on Networks of Workstations.  (1998.ICDCS.ps.gz).
  72. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction -Based Systems.  (1998.PDTA.RVM_EXODUS.ps.gz).
  73. Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1998). On Using Network RAM as a non-volatile Buffer.  (1998.TR227.NVRAM.ps.gz).
  74. Flouris, M.D., & Markatos, E.P. (1998). The Network RamDisk : Using Remote Memory on Heterogeneous NOWs.  (1998.TR226.nrd_TR.ps.gz).
  75. Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations.  (1998.CANPC98.REQ.ps.gz).
  76. Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS I: A Single-chip ATM switch for NOWs.  (1997.CANPC97.ATLAS.ps.gz).
  77. Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed.  (1997.HPCS97.drain_cr_buf.ps.gz).
  78. Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., Magklis, G.I., Milolidakis, G., & Oikonomou, Th. (1997). Issues in the Design and Implementation of User-Level DMA.  (1997.TR182.UDMA.ps.gz).
  79. Papathanasiou, A E., & Markatos, E.P. (1997). Lightweight Transactions on Networks of Workstations.  (1997.TR209.Lightweight_Transactions_on_NOWs.ps.gz).
  80. Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-Queue Management and Scheduling for Improved QoS in Communication Networks.  (1997.EMMSEC.Muqpro.ps.gz).
  81. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1997). On using Network Memory to Improve the Performance of Transaction-Based Systems.  (1997.TR190.Remote_memory_RVM.ps.gz).
  82. Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.  (1997.ARVLSI.Pipe_MultiQueue.ps.gz).
  83. Artavanis, M. (1997). Simulation of the Shared Disks Architecture for Transaction Processing Systems.  (1997.TR211.Simulation_SharedDisks_Archit_Transaction_Processing_Systems.ps.gz).
  84. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching Fabrics with Internal Backpressure using the ATLAS I Single-Chip ATM Switch.  (1997.GLOBECOM.ATLAS_I_Fabrics.ps.gz).
  85. Markatos, E.P., & Katevenis, M.G.H. (1997). User-Level DMA without Operating System Kernel Modification.  (1997.HPCA97.user_level_dma.ps.gz).
  86. Markatos, E.P. (1997). Visualizing Working Sets.  (1997.TR192.Visualizing_working_sets.ps.gz).
  87. Markatos, E.P., & Chronaki, C. (1996). A Top-10 Approach to Prefetching on the Web.  (1996.TR173.Web_Prefetching.ps.gz).
  88. Nikolaou, Ch., Markatos, E.P., Karavassili, M., & Saridakis, T. (1996). ArrayTracer: A Parallel Performance Analysis Tool.  (1996.TR162.ArrayTracer_A_Parallel_Performance_Analysis_Tool.ps.gz).
  89. Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control.  (1996.HOTI.ATLAS_I_ATMswitchChip.ps.gz).
  90. Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure.  (1996.EMSYS96.ATLAS_I_ATMswitchHIC.ps.gz).
  91. Spyridakis, E. (1996). Comparison of Credit Based ATM and Wormhole Under Bursty Traffic or With Hot Spots.  (1996.TR170.ATM_vs_Wormhole_in_Greek.ps.gz).
  92. Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-Flow-Controlled ATM over HIC Links in the ASICCOM ''ATLAS I"" Single-Chip Switch.  (1996.RTMagazine.ATLAS_I_ATMswitchChip.ps.gz).
  93. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1996). Credit-Flow-Controlled ATM versus Wormhole Routing.  (1996.TR171.ATM_vs_Wormhole.ps.gz).
  94. Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager.  (1996.usenix.ps.gz).
  95. Markatos, E.P. (1996). Issues in Reliable Network Memory Paging.  (1996.MASCOTS96.Reliable_Network_Memory.ps.gz).
  96. Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos :High-Performance Networking for Parallel Processing on Workstation Clusters..  (1996.HPCA96.Telegraphos.ps.gz).
  97. Kozyrakis, Ch. (1996). The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch.  (1996.TR172.QueueManagement.ps.gz).
  98. Markatos, E.P. (1996). Using Remote Memory to avoid Disk Thrashing: A Simulation Study.  (1996.MASCOTS96.Remote_memory_paging.ps.gz).
  99. Efthymiou, A. (1995). Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-custom CMOS.  (1995.TR143.Design_Implementation_25Gbs_PipelinedMem_Switch_Buffer.ps.gz).
  100. Markatos, E.P., Dramitinos, G., & Papachristos, K. (1995). Implementation and Evaluation of a Remote Memory Pager.  (1995.TR129.remote_memory_paging.ps.gz).
  101. Labrinidis, A. (1995). Methods to cluster transactions into utilization classes with similar workload characteristics.  (1995.TR135.Methods_cluster_transactions_similar_workload_characteristics.ps.gz).
  102. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches.  (1995.SIGCOMM95.PipeMemoryShBuf.ps.gz).
  103. Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch.  (1995.HOTI.VCflowCtrlTeleSwitch.ps.gz).
  104. Xanthaki, Z. (1994). A Memory Controller for Access Interleaving over a single Rambus.  (1994.TR124.RAMBUS_AccessInterleaving_MemoryController.ps.gz).
  105. Chatzaki, M. (1994). A Translation Scheme Between Two Real-Time Formalisms.  (1994.TR128.specification_automatic_verification_timed_automata.ps.gz).
  106. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG Image Compression.  (1994.TR114.Arithmetic_Entropy_Codec_VLSI_chip_for_JPEG.ps.gz).
  107. Katevenis, M.G.H. (1994). FORTH, ICS: Computer Architecture and VLSI Systems Group: A Profile.  (1994.AVG_PROFILE.ps.Z).
  108. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1994). Pipelined Memory Organization for High Performance Switching and Buffering.  (1994.TR127.PipelinedMemory.ps.Z).
  109. Katevenis, M.G.H. (1994). Telegraphos: High-Speed Communication Architecture for Parallel and Distributed Computer Systems.  (1994.TR123.Telegraphos.ps.Z).
  110. Markatos, E.P., & Chronaki, C. (1994). Using reference counters in Update Based Coherent Memory.  (1994.PARLE94.Reference_Counters.ps.Z).
  111. Markatos, E.P. (1993). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors.  (1993.PARCO93.Architecture_infuence_on_Scheduling.ps.Z).
  112. Markatos, E.P., & Leblanc, Th.J. (1993). Locality-Based Scheduling in Shared-Memory Multiprocessors.  (1993.TR94.Locality_Based_Scheduling.ps.Z).
  113. Markatos, E.P., & Chronaki, C. (1993). Trace-Driven Simulation of Data-Alignment and other Factors affecting Update and Invalidate Based Coherent Memory.  (1993.TR93.DATA_ALIGNMENT_IN_VIRTUAL_SHARED_MEMORY.ps.Z).
  114. Markatos, E.P., & LeBlanc, T.J. (1993). Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors.  (1993.TPDS.Affinity_Loop_Scheduling.ps.Z).
  115. Vatsolaki, P. (1992). Design of a High-Speed UART VLSI Library Cell.  (1992.TR50.High_Speed_UART_VLSIlibCell.ps.Z).
  116. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip : Architecture and Feasibility Study.  (1991.TR025_General_Purpose_ATM_Switch_Chip.pdf).
  117. Sidiropoulos, S. (1991). Fast Packet Switches for Asynchronous Transfer Mode.  (1991.TR25.Fast_packet_switches.ps.Z).
  118. Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broad-Band Networks.  (1987.TR001_Fast-Switching_Fair-Control_Broad-Band-Networks.pdf).

M.S. Theses

  1. Kalyvianakis, G. (2022). An Efficient OpenSHMEM Implementation. 
  2. Nikoloudakis, M. (2022). Design and Implementation of a Write Based version of the Exanet MPI. 
  3. Oikonomidou, M. (2022). Multi-layer bipartite structural features to analyze YouTube Social Network. March 2022.
  4. Mousouros, O. (2022). Stream communication across RISC-V Coherence Islands, with Read-Invalidate and Write-through-Combine Cache Policies. 
  5. Xanthakis, G. (2021). Balancing Garbage Collection vs I/O Amplification using hybrid Key-Value Placement in LSM-based Key-Value Stores. July 2021.
  6. Mastorakis, I. (2021). Design and implementation of a scalable IOMMU for RISC-V architectures. July 2021.
  7. Totomis, S. (2021). Design and implementation of cache coherence engines for RISC-V systems. November 2021.
  8. Giortamis, E. (2021). Elastic resource allocation for a structural design application. July 2021.
  9. Katevenis Bitzos, G. (2021). Hierarchical shared address space MPI Collectives, for multi/many-core processors. November 2021.
  10. Vardoulakis, M. (2021). Tebis: efficient index replication for persistent LSM-based key-value stores. November 2021.
  11. Kolokasis, I.G. (2021). TeraCache: efficient Spark caching over fast storage devices. March 2021.
  12. Giaourtas, M. (2020). Design-space exploration of FPGA architectures for efficient HPC acceleration. March 2020.
  13. Kiosterakis, Ch. (2020). Efficient implementations of concurrent snapshot objects. March 2020.
  14. Kalaentzis, G. (2020). Embedding key-value stores in object and database services. November 2020.
  15. Mageiropoulos, E. (2020). Implementing convolutional neural networks in a cluster of interconnected FPGAs using Vivado HLS. November 2020.
  16. Xirouchakis, P. (2019).  Design and Implementation of the Send Part of an Advanced RDMA Engine. July 2019.
  17. Papavasileiou, E. (2019). Concurrent lock-free binary search tree implementations with range query support. July 2019.
  18. Psistakis, A. (2019). Handling of memory page faults during virtual-address RDMA. November 2019.
  19. Mikrou, S. (2019). Power and performance analysis of key-value stores on ARM and x86 based servers. November 2019.
  20. Vardas, I. (2019). Process placement optimizations and heterogeneity extensions to the Slurm resource manager. November 2019.
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  27. Papakonstantinou, N. (2015). Combining Recursively Parallel Runtimes with Blocked-based Dependence Analysis. 
  28. Papoulas, C. (2015). Design and Implementation of a Social Networking Architecture for Cloud Deployment Specialists. 
  29. Glenis, A. (2015). FT-Myrmics : A fault tolerant runtime system for task based programming models. 
  30. Poulios, P.D. (2015). Low-latency implementation of network sockets over remote DMA. July 2015.
  31. Velegrakis, J.V. (2015). Operating system mechanisms for remote resource utilization in ARM microservers. July 2015.
  32. Papagiannis, A. (2013). Implementing Scalable Parallel Programming Models with Hybrid Address Spaces. 
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  35. Papatriantafyllou, A. (2012). Efficient and Accurate Block-Level Dependence Analysis For Task Dataflow Models. 
  36. Zakkak, F. S. (2012). SCOOP: Language extensions and compiler optimizations for task-based programming models. 
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  38. Tsaliagkos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol. 
  39. Saloustros, G. (2011). Design and Implementation of a Scalable Storage System for Fully-Consistent Replicated Data Logging. 
  40. Kesapidis, I. (2011). Dynamic Dependence Analysis on Multi-core Processors. 
  41. Fountoulakis, M. (2010). DARC: Design and Evaluation of an I/O Controlller for data Protection. May 2010.
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  43. Koukos, K. (2010). Locality management in task-based parallel programming models. August 2010.
  44. Zampetakis, M. (2010). Runtime support for programming explicit communication chip multiprocessors. July 2010.
  45. Sempepou, Z. (2010). Scalable storage support and fault-tolerance for data stream processing systems. July 2010.
  46. Katsamali, M. (2010). Software implementation of MPI primitives in multicore FPGA. June 2010.
  47. Makatos, A. (2010). ZBD: Using Transparent Compression at the Block Level to Increase Storage Space Efficiency. March 2010.
  48. Nikiforos, G. (2009). FPGA implementation of a cache controller with configurable scratchpad space. April 2009.
  49. Tzenakis, G. (2009). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the Cell Processor. November 2009.
  50. Kasapaki, E. (2008). An EDA Tool for the Timing Analysis, Optimization and Timing Validation of Asynchronous Circuits. 2008.
  51. Passas, S. (2008). Analysis and Optimization of Overheads in Communication Protocols Over High Speed Ethernet-based Cluster Interconnects. April 2008.
  52. Mangas, E. (2008). Fine-grained Localization in Wireless Sensor Networks using Acoustic Sound Transmissions and High Precision Clock Synchronization. December 2008.
  53. Aslanidis, I. (2008). Multi-valued logic synthesis. April 2008.
  54. Pantelias, E. (2008). Αποσυγχρονισμός Βιομηχανικών Κυκλωμάτων. April 2008.
  55. Michelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. September 2007.
  56. Matthaiakis, P. (2007). Gated Dual-Rail - A Methodology for Reducing the Power Consumption of Monotonic Dual-Rail Circuits. December 2007.
  57. Papamichail, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. September 2007.
  58. Andrikos, N. (2006). A Fully-Automated Desynchronization Flow for Synchronous Circuits. April 2006.
  59. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. April 2006.
  60. Kotsis, G. (2006). Improving Scalability on Shared Memory Clusters. December 2006.
  61. Passas, G. (2006). Packet Mode Scheduling in Buffered Crossbar Switches. April 2006.
  62. Panagiotakis, G. (2006). Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams. September 2006.
  63. Giannakopoulos, I. (2005). CORMOS: A Communication-Oriented Runtime System for Wireless Sensor Networks. April 2005.
  64. Papaefstathiou, V. (2005). Design and Implementation of Network Packet Classification Engines. April 2005.
  65. Dokianaki, O. (2005). Evaluation of Asynchronous Interconnect Techniques for Digital SoC. April 2005.
  66. Xynidis, D. (2005). Performance Analysis and Scaling of Networked Shared Block-Level Storage. December 2005.
  67. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. December 2005.
  68. Simos, D.G. (2004). Design of a 32x32 Variable Packet-Size Buffered Crossbar Switch Chip. November 2004.
  69. Xynidis, K. (2004). Network Intrusion Prevention on Multilevel Processing Architectures. November 2004.
  70. Sarmpanis, A. (2004). Ένα Πρωτόκολλο Εκμισθώσεων για την Ενημέρωση Δεδομένων Προσωρινών Μνημών peer-to-peer δικτύων. November 2004.
  71. Charitakis, I. (2004). Εφαρμογές του Επεξεργαστή Δικτύων IXP 1200 σε Συστήματα Ανίχνευσης Εισβολέων για Δίκτυα. April 2004.
  72. Papachristos, Ch. (2002).  Navigation Technologies over low bandwidth links for Thin Clients An introduction to the CC/PP protocol. December 2002.
  73. Kapsalis, D. (2002). Design and Implementation of a per-Flow Queue Manager of an ATM Switch using FPGA Technology. March 2002.
  74. Charteros, K. (2002). Fast Parallel Comparison Circuis for Scheduling. March 2002.
  75. MeÃntanis, D. (2002). Hardware Conversion and Software Import to a Prototype Microprocessor Board. December 2002.
  76. Kalyvianaki, E. (2002). Î§-PacketQ a network tragic visualization tool. A reial-time approach for multiple users. December 2002.
  77. Lymperis, S. (2002). Implementation of a Motion Compensaation Subsystem for an MPEG-II Decoder. December 2002.
  78. Chrysos, N. (2002). Weighted Max-Min Fair Scheduling, for a Crossbar, with Small Internal Memory. 2002.
  79. Sapountzis, G. (2002). Πλέγματα Μεταγωγής BENES με Εσωτερικό Backpressure Πολυπλοκότητας O(N). December 2002.
  80. Papadakis, G. (2001). Design and FPGA Implementation of an ABR traffic scheduler and utopia interfaces for an ATM network switch. November 2001.
  81. Gialama, A. (2001). Distributed Video Server with Quality of Service. June 2001.
  82. Asimakopoulou, X.A. (2001). Effective Resource Discovery on the World Wide Web. June 2001.
  83. Danalis, A. (2001). Firewall development for the embedded network processor IXP1200. July 2001 .
  84. Lolas, Ch. (2001). Low Level Software Design and Implementation for High Performance Packet Switches. November 2001.
  85. Ioannou, A. (2000). An ASIC Core for Pipelining Heap Management to Support Scheduling in High Speed Networks. November 2000.
  86. Oikonomou, A. (2000). Architecture and Implementation of an Adaptation Bridge for ATM Networks. June 2000.
  87. Flouris, M.D. (2000). Design & Implementation of Methods Enchancing the Performance of www Proxies. March 2000.
  88. Nikologiannis, A. (2000). Efficient Per-Flow Queuing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques. November 2000.
  89. Sidiropoulos, A. (1999). Distributed Indexing and Searching Mechanisms. March 1999.
  90. Chatzistamatiou, A. (1999). EasyAgent: a Masif Compliant Environment for Mobile Java Objects. March 1999.
  91. Papathanasiou, A E. (1999). Effective Resource Discovery on the World Wide Web. June 1999.
  92. Milolidakis, G. (1999). MemSpyer: A Performance Debugging Tool which simulates and visualizes memory hierarchy. March 1999.
  93. Glykopoulos, G. (1998). Design and Ιmplementation of an 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. July 1998.
  94. Karakonstantis, P. (1998). Efficient Memory Management for high-speed ATM networks. November 1998.
  95. Kornaros, G. (1997).  Implementation of Pipelined Multi- Queue Management in the ATLAS I Switch in Full- Custom CMOS VLSI. June 1997.
  96. Zarras, A. (1997). Array Tracer : Parallel Performance Analysis and Visualization. March 1997.
  97. Gkanas, L. (1997). New Caching ways in the World Wide Web. 1997.
  98. Terzis, S. (1997). Performance Monitoring in Digital Library Systems. November 1997.
  99. Artavanis, M. (1997). Simulation of the Shared Discks Architecture for Transaction Processing Systems. November 1997.
  100. Moraiti, M. (1997). Trace-driven Simulation of ATM and Wormhole networks. November 1997.
  101. Anastasiadi, A. (1996).  A study of Microeconomic Algorithms for Load Balancing and Data Replication in Distributed Computer Systems. November 1996.
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  103. Papachristos, K. (1996). Design and Implementation of the Telegraphos Operations for the Mach Operating System. March 1996.
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  109. Lamprinidis, A. (1995). Μέθοδοι Ταξινόμησης Δοσοληψιών σε Ομάδες με Παρόμοια Χαρακτηριστικά Φόρτου Εργασίας. November 1995.
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  113. Farsaris, I. (1993). Design and Implementation of undo-redo mechanism in Labyrinth System. May 1993.
  114. Karydis, N. (1993). Βιβλιοθήκη Γεωμετρικών Κυττάρων και Μετασχηματισμών για τον Λαβύρινθο. April 1993.
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  118. Vatsolaki, P. (1992). Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI. 1992.
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Ph.D. Theses

  1. Papagiannis, A.P (2021). Memory-mapped I/O for fast storage. March 2021.
  2. Zakkak, F. S. (2017). Java™ on Scalable Memory Architectures. March 2017.
  3. Lyberis, S. (2013). Myrmics: a scalable runtime system for global address spaces. 
  4. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars. 
  5. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors. 
  6. Chrysos, N. (2007). Request- Grant Scheduling for Congestion Elimination in Multistage Networks. May 2007.
  7. Marazakis, E. (2000). Service Composition and Service- level Agreements in Open Distributed Systems. December 2000.

Other Technical Reports

  1. Faith, E., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2012). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-Freedom. 
Found: 249 publications